Multi-chip package for reducing test time

Abstract

A multi-chip package is provided. The multi-chip package includes semiconductor chips. The multi-chip package receives selection signals for selecting two or more chips in response to the selection signals. Any number of chips may be simultaneously selected for a test and the test time can be reduced.

1 . A multi-chip package comprising:
 a plurality of chips; and   an instruction set signal port to receive an instruction set signal to select one or more chips in response to an instruction set in such an instruction set signal.   
   
   
       2 . The multi-chip package according to  claim 1 , further comprising an MSB address pin to receive a selection signal for selecting one of the plurality of chips, wherein at least two chips are selected in response to the instruction set signal and the selection signal. 
   
   
       3 . The multi-chip package according to  claim 2 , wherein each of the chips comprises:
 at least one instruction set signal input terminal to receive the instruction set signal;   an MSB address input terminal to receive the selection signal; and   a chip selection unit to generate a chip selection signal in response to the selection signal and the instruction set signal.   
   
   
       4 . The multi-chip package according to  claim 3 , comprising:
 a first chip enabled when the chip selection signal of the first chip has a first voltage level; and   a second chip enabled when the chip selection signal of the second chip has a second voltage level.   
   
   
       5 . A multi-chip package comprising:
 a plurality of chips;   a first selection signal port to receive a first selection signal to select one of the plurality of chips; and   a high voltage signal port to receive a high voltage signal, and to select at least two chips in response to the high voltage signal and the first selection signal.   
   
   
       6 . The multi-chip package according to  claim 5 , wherein each of the chips comprises:
 a selection signal input terminal to receive the first selection signal;   a high voltage input terminal to receive the high voltage signal;   a selection signal generation unit to generate a second selection signal in response to the high voltage signal; and   an OR gate to perform an OR operation on the first selection signal and the second selection signal, and to output a chip selection signal for the chip.   
   
   
       7 . The multi-chip package according to  claim 6 , comprising:
 a first chip enabled when the chip selection signal of the first chip has a first voltage level; and   a second chip enabled when the chip selection signal of the second chip has a second voltage level.