Structure and process integration for flash storage element and dual conductor complementary mosfets

Abstract

A method is provided for simultaneously fabricating a flash storage element, an NFET and a PFET having metal gates with different workfunctions. A first gate metal layer of the NFET having a first workfunction is deposited simultaneously with a first metal layer for forming the floating gate of the flash storage element. A second gate metal layer of the PFET having a second workfunction different from the first workfunction is deposited simultaneously with a second metal layer for forming the control gate of the flash storage element. A semiconductor layer is deposited over the first and second metal layers and gate metal layers and patterned to form first, second and third gates. Source and drain regions of the flash storage element, the NFET and the PFET are formed adjacent to the first, second and third gates, respectively.

1 . A method of simultaneously fabricating a flash storage element, an n-type field effect transistor (FET) and a p-type FET of a semiconductor element, comprising:
 (a) depositing a first gate dielectric and a first gate metal layer overlying the first gate dielectric and patterning the first gate metal layer with the first gate dielectric to overlie first and second active semiconductor areas of a substrate but not overlie a third active semiconductor area of the substrate;   (b) depositing a second gate dielectric and a second gate metal layer overlying the second gate dielectric and patterning the second gate metal layer with the second gate dielectric to overlie the first and third active semiconductor areas but not overlie the second active semiconductor area;   (c) simultaneously forming first, second and third gates overlying the first, second and third active semiconductor areas, respectively, by processing including depositing and patterning a semiconductor layer; and   (d) forming source and drain regions of the flash storage element, the n-type FET and the p-type FET in the first, second and third active semiconductor areas, respectively.   
   
   
       2 . The method as claimed in  claim 1 , wherein the flash storage element has a floating gate including a portion of the first gate metal layer and a control gate including a portion of the second gate metal layer, the first and second gate metal layers being separated by the second gate dielectric layer. 
   
   
       3 . The method as claimed in  claim 2 , wherein the gate length of the floating gate is greater than the gate length of the control gate. 
   
   
       4 . The method as claimed in  claim 2 , wherein the gate length of at least one of the control gate or the floating gate of the flash storage element is greater than the gate length of at least one of the second or third gates. 
   
   
       5 . The method as claimed in  claim 2 , wherein the first gate metal layer has a first workfunction and the second gate metal layer has a second workfunction substantially different from the first workfunction. 
   
   
       6 . The method as claimed in  claim 2 , wherein step (a) determines locations of edges of the floating gate and step (b) determines locations of edges of the control gate independently from the processing in step (a). 
   
   
       7 . The method as claimed in  claim 5 , wherein the first gate dielectric includes a dielectric layer having a dielectric constant substantially greater than a dielectric constant of silicon dioxide. 
   
   
       8 . The method as claimed in  claim 7 , wherein the first gate dielectric includes at least one dielectric material selected from the group consisting of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), strontium titanate (SrTiO 3 ), and lanthanum aluminate (LaAlO 3 ). 
   
   
       9 . The method as claimed in  claim 7 , wherein the second gate dielectric includes a dielectric layer having a dielectric constant substantially greater than a dielectric constant of silicon dioxide. 
   
   
       10 . The method as claimed in  claim 9 , wherein the second gate dielectric includes at least one dielectric material selected from the group consisting of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), strontium titanate (SrTiO 3 ), and lanthanum aluminate (LaAlO 3 ). 
   
   
       11 . A semiconductor element including a flash storage element, an n-type field effect transistor (FET) and a p-type FET, comprising:
 a single-crystal semiconductor substrate having a major surface and first, second and third active semiconductor areas exposed at the major surface, each of the first, second and third active semiconductor areas being separated by isolation regions extending from the major surface inwardly into the substrate; and   a flash storage element having a conduction channel within the first active semiconductor area, the n-type FET having a conduction channel within the second active semiconductor area and the p-type FET having a conduction channel within the third active semiconductor area, the flash storage element having a floating gate including a portion of a first gate metal layer and a control gate including a portion of a second gate metal layer, the n-type FET having a gate including a portion of the first gate metal layer and the p-type FET having a gate including a portion of the second gate metal layer, wherein the first and second gate metal layers have first and second different workfunctions.   
   
   
       12 . A semiconductor element as claimed in  claim 11 , wherein the flash storage element is operable to nonvolatilely store an electrically alterable state for controlling operation of a function of the semiconductor element. 
   
   
       13 . The semiconductor element as claimed in  claim 12 , wherein the n-type FET has a gate dielectric including a portion of a first gate dielectric layer and the p-type FET has a gate dielectric including a portion of a second gate dielectric layer, wherein the floating gate and the control gate of the flash storage element are separated by a portion of the second gate dielectric layer. 
   
   
       14 . The semiconductor element as claimed in  claim 13 , wherein the gate length of the floating gate is greater than the gate length of the control gate. 
   
   
       15 . The semiconductor element as claimed in  claim 14 , wherein locations of edges of the control gate are independent from locations of edges of the floating gate. 
   
   
       16 . The semiconductor element as claimed in  claim 13 , wherein the gate length of at least one of the control gate or the floating gate of the flash storage element is greater than the gate length of at least one of the second or third gates. 
   
   
       17 . The semiconductor element as claimed in  claim 16 , wherein one of the first and second gate metal layers includes titanium nitride and another one of the first and second gate metal layers includes tantalum nitride. 
   
   
       18 . The semiconductor element as claimed in  claim 17 , wherein the first gate dielectric layer includes a dielectric layer having a dielectric constant substantially greater than a dielectric constant of silicon dioxide. 
   
   
       19 . The semiconductor element as claimed in  claim 17 , wherein the second gate dielectric layer includes a dielectric layer having a dielectric constant substantially greater than a dielectric constant of silicon dioxide. 
   
   
       20 . The semiconductor element as claimed in  claim 17 , wherein at least one of the first and second gate dielectric layers includes at least one dielectric material selected from the group consisting of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), lanthanum oxide (La 2 O 3 ), strontium titanate (SrTiO 3 ), and lanthanum aluminate (LaAlO 3 ).