Transistor and method for manufacturing thereof

Abstract

A transistor includes a gate insulating layer over a semiconductor substrate; a first insulating layer on both sides of the gate insulating layer; first spacers over the first insulating layer and being spaced apart from each other; and a gate conductive plug between the first spacers. A method for manufacturing a transistor includes sequentially depositing a first insulating layer and a second insulating layer over a semiconductor substrate; etching the second insulating layer; implanting impurity ions; depositing and etching a layer of spacer material to form first spacers; removing a first portion of the first insulating layer between the first spacers; depositing a gate insulating layer the place of the first portion of the first insulating layer; forming a gate conductive plug on the gate insulating layer; forming second spacers on sidewalls of the gate conductive plug; and forming a silicide on an upper surface of the gate conductive plug.

1 . A transistor comprising:
 a gate insulating layer over a semiconductor substrate;   a first insulating layer over the semiconductor substrate on both sides of the gate insulating layer;   first spacers over the first insulating layer, the first spacers being spaced apart from each other by a predetermined distance;   a gate conductive plug between the first spacers; and   a silicide layer over an upper surface of the gate conductive plug,   wherein a thickness ratio between the first insulating layer and the silicide layer is in a range of about 1:4 to 1:6.   
   
   
       2 . The transistor according to  claim 1 , wherein at least one of the gate insulating layer and the first insulating layer has a thickness of 20±5 Å. 
   
   
       3 . (canceled) 
   
   
       4 . The transistor according to  claim 1 , wherein the silicide layer has a thickness of 100±20 Å. 
   
   
       5 - 20 . (canceled) 
   
   
       21 . The transistor according to  claim 1 , wherein the first spacers are formed before the gate insulating layer is deposited. 
   
   
       22 . The transistor according to  claim 1 , wherein the gate insulating layer and first insulating layer have an equal thickness. 
   
   
       23 . The transistor according to  claim 1 , further comprising a halo/pocket region under the gate insulating layer. 
   
   
       24 . The transistor according to  claim 1 , further comprising second spacers formed on side walls of the gate conductive plug and having the first spacers formed thereon. 
   
   
       25 . The transistor according to  claim 1 , wherein the first spacers comprise nitride. 
   
   
       26 . The transistor according to  claim 1 , wherein the gate conductive plug comprises polysilicon. 
   
   
       27 . The transistor according to  claim 24 , wherein the second spacers comprise one of nitride and oxide. 
   
   
       28 . The transistor according to  claim 1 , wherein the silicide layer comprises a silicide material selected form the group consisting of Ti, Co, and Ni.