CMOS transistor using germanium condensation and method of fabricating the same

Abstract

Provided is a CMOS transistor formed using Ge condensation and a method of fabricating the same. The CMOS transistor may include an insulating layer, a silicon layer on the insulating layer and including a p-MOS transistor region and an n-MOS transistor region, a first gate insulating layer and a first gate on a channel region of the p-MOS transistor region, and a second gate insulating layer and a second gate on a channel region of the n-MOS transistor region, wherein a source region and a drain region of the p-MOS transistor region may be tensile-strained due to Ge condensation, and the channel region of the n-MOS transistor region may be tensile-strained due to the Ge condensation.

1 . A CMOS transistor comprising:
 an insulating layer;   a silicon layer on the insulating layer and including a p-MOS transistor region and an n-MOS transistor region;   a first gate insulating layer and a first gate on a channel region of the p-MOS transistor region; and   a second gate insulating layer and a second gate on a channel region of the n-MOS transistor region,   wherein a source region and a drain region of the p-MOS transistor region are tensile-strained due to Ge condensation, and the channel region of the n-MOS transistor region is tensile-strained due to the Ge condensation.   
   
   
       2 . The CMOS transistor of  claim 1 , wherein the channel region of the p-MOS transistor region is compressive-strained. 
   
   
       3 . The CMOS transistor of  claim 1 , wherein the length of the tensile-strained region is extended by about 0.1 to 2%. 
   
   
       4 . The CMOS transistor of  claim 1 , wherein the channel region of the p-MOS transistor region is a region in which Ge is condensed, and the channel region of the p-MOS transistor region has a Ge mole fraction smaller than those of the source region and the drain region of the p-MOS transistor region. 
   
   
       5 . The CMOS transistor of  claim 1 , wherein the first and second gate insulating layers are formed of silicon oxide or a dielectric material having a dielectric constant greater than that of the silicon oxide. 
   
   
       6 . The CMOS transistor of  claim 1 , wherein the first and second gates are formed of polysilicon or a metal. 
   
   
       7 . The CMOS transistor of  claim 1 , wherein the p-MOS transistor and the n-MOS transistor have a fin structure, a trigate structure, an omega gate structure, or a gate-all-around structure. 
   
   
       8 . A method of fabricating a CMOS transistor using Ge condensation, the method comprising:
 providing a substrate having an insulating layer and a silicon layer on the insulating layer;   patterning the silicon layer into a p-MOS transistor region and an n-MOS transistor region;   forming a mask layer on the substrate using a dielectric material to cover the p-MOS transistor region and the n-MOS transistor region;   exposing a source region and a drain region of the p-MOS transistor region and a channel region of the n-MOS transistor region through the mask layer;   coating a SiGe layer on the substrate to cover the source region and the drain region of the p-MOS transistor region and the channel region of the n-MOS transistor region; and   condensing Ge of the SiGe layer in the source region and the drain region of the p-MOS transistor region and the channel region of the n-MOS transistor region by oxidizing the SiGe layer.   
   
   
       9 . The method of  claim 8 , wherein the channel region of the p-MOS transistor region has greater compressive-strain compared to the source region and the drain region of the p-MOS transistor region, and the channel region of the n-MOS transistor region is tensile-strained. 
   
   
       10 . The method of  claim 8 , wherein the dielectric material is silicon nitride. 
   
   
       11 . The method of  claim 8 , wherein coating the SiGe layer is performed using a sputtering method or a chemical vapor deposition method. 
   
   
       12 . The method of  claim 11 , wherein the condensation of Ge of the SiGe layer in the silicon layer extends a length of the corresponding silicon layer where the condensation of Ge is performed, by about 0.1 to about 2%. 
   
   
       13 . The method of  claim 8 , wherein patterning the silicon layer into the p-MOS transistor region further comprises:
 coating a second SiGe layer on the p-MOS transistor region; and   condensing Ge of the second SiGe layer in the source region, the drain region, and the channel region of the p-MOS transistor region by oxidizing the second SiGe layer.   
   
   
       14 . The method of  claim 13 , wherein oxidizing the second SiGe layer includes annealing the substrate in a furnace at a temperature of about 800 to about 950° C. for about a few minutes to about one hour while supplying oxygen into the furnace. 
   
   
       15 . The method of  claim 8 , wherein the p-MOS transistor and the n-MOS transistor have a fin structure, a trigate structure, an omega gate structure, or a gate-all-around structure.