US2009259696A1PendingUtilityA1

Node Synchronization for Multi-Processor Computer Systems

Assignee: SILICON GRAPHICS INCPriority: Apr 25, 2005Filed: Dec 8, 2008Published: Oct 15, 2009
Est. expiryApr 25, 2025(expired)· nominal 20-yr term from priority
G06F 15/16
53
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Claims

Abstract

A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.

Claims

exact text as granted — not AI-modified
1 . An apparatus for controlling access by a set of accessing nodes to shared memory of a home node, the home node and accessing nodes being part of a multi-node shared-memory computer system, the apparatus comprising:
 means for determining that each node in the set of nodes has accessed the shared memory; and   means for forwarding a completion message to each node in the set of nodes after it is determined that each node has accessed the shared memory, the completion message having data indicating that each node in the set of nodes has accessed the shared memory of the home node.

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