Semiconductor device, manufacturing method thereof, and data processing system

Abstract

A miniaturized semiconductor device is provided by reducing the design thickness of a wiring line protecting film covering the surface of a wiring layer, and reducing the distance between the wiring layer and via plugs formed by a self-aligning process. Dummy mask layers extending in the same layout pattern as the wiring layer is formed above the wiring layer covered with a protecting film composed of a cap layer and side wall layers. In the self-aligning process for forming via plugs in a self-aligned manner with the wiring layer and its protecting film, the thickness of the cap layer is reduced and the design interval between the via plugs is reduced, whereby the miniaturization of the semiconductor device is achieved.

1 . A semiconductor device comprising:
 a wiring layer including a plurality of wiring lines, the surface of each of which is covered with an insulation protecting film, the entire of the wiring layer being covered with an interlayer insulation film;   a plurality of dummy insulation films made of a different material from that of the first interlayer insulation film, and extending, above the first interlayer insulation film, in the same layout as that of the plurality of wiring lines; and   a conductive plug passing through the interlayer insulation film between two adjacent wiring lines of the plurality of wiring lines, the conductive plug being formed in self-aligned manner with the two adjacent wiring lines and the insulation protecting film corresponding thereto.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , wherein the conductive plug is formed in a self-aligned manner with two adjacent dummy insulation films formed above the two adjacent wiring lines. 
     
     
         3 . The semiconductor device as claimed in  claim 1 , wherein the insulation protecting film is made of a silicon nitride film, and the first interlayer insulation film is made of a silicon oxide film. 
     
     
         4 . The semiconductor device as claimed in  claim 2 , wherein the insulation protecting film is made of a silicon nitride film, and the interlayer insulation film is made of a silicon oxide film. 
     
     
         5 . The semiconductor device as claimed in  claim 1 , wherein the semiconductor device is formed as a DRAM device. 
     
     
         6 . The semiconductor device as claimed in  claim 2 , wherein the semiconductor device is formed as a DRAM device. 
     
     
         7 . The semiconductor device as claimed in  claim 6 , wherein the plug connects a landing pad formed in an upper wiring layer and a lower electrode formed in a lower wiring layer; and wherein an capacitor is formed on the landing pad. 
     
     
         8 . The semiconductor device as claimed in  claim 2 , wherein the semiconductor device is formed as a logic circuit. 
     
     
         9 . The semiconductor device as claimed in  claim 8 , wherein the plug connects a signal wiring line formed in an upper wiring layer and a signal wiring line formed in a lower wiring layer. 
     
     
         10 . The semiconductor device as claimed in  claim 2 , wherein the semiconductor device is formed as a combination device having both a DRAM circuit and a logic circuit. 
     
     
         11 . The semiconductor device as claimed in  claim 1 , wherein the insulation protecting film includes a cap layer covering the top of each of the plurality of wiring lines and side wall layers covering the sides of each of the plurality of wiring lines, and the plurality of dummy insulation films each include a central portion extending above the cap layer, and side portions extending above the side wall layers. 
     
     
         12 . The semiconductor device as claimed in  claim 2 , wherein the insulation protecting film includes a cap layer covering the top of each of the plurality of wiring lines and side wall layers covering the sides of each of the plurality of wiring lines, and the plurality of dummy insulation films each include a central portion extending above the cap layer, and side portions extending above the side wall layers. 
     
     
         13 . The semiconductor device as claimed in  claim 1 , further comprising an upper interlayer insulation film for covering the dummy insulation films, wherein a capacitor connected to the conductive plug is formed within the second interlayer insulation film. 
     
     
         14 . The semiconductor device as claimed in  claim 2 , further comprising an upper interlayer insulation film for covering the dummy insulation films, wherein a capacitor connected to the conductive plug is formed within the second interlayer insulation film. 
     
     
         15 . A data processing system having a data processor and a memory connected to the data processor, wherein the memory comprises:
 a wiring layer including a plurality of wiring lines 1  the surface of each of which is covered with an insulation protecting film, the entire of the wiring layer being covered with a first interlayer insulation film;   a plurality of dummy insulation films made of a different material from that of the first interlayer insulation film, and extending, above the first interlayer insulation film, in the same layout as that of the plurality of wiring lines; and   a conductive plug passing through the first interlayer insulation film between two adjacent wiring lines of the plurality of wiring lines, the conductive plug being formed in self-aligned manner with the two adjacent wiring lines and the insulation protecting film corresponding thereto.   
     
     
         16 . A manufacturing method of a semiconductor device comprising:
 forming a wiring layer including a plurality of wiring lines, the surface of each of which is covered with an insulation protecting film;   forming an interlayer insulation film to cover the wiring layer;   forming dummy insulation films extending above the interlayer insulation film, in the same layout as that of the plurality of wiring lines;   forming a via hole passing through the interlayer insulation film, in a self-aligned manner with the plurality of wiring lines and the insulation protecting film covering the plurality of wiring lines; and   forming a via plug within the via hole.   
     
     
         17 . The manufacturing method of a semiconductor device as claimed in  claim 16 , wherein the forming a via hole includes forming the via hole in a self-aligned manner with two adjacent dummy insulation films formed above the two adjacent wiring lines. 
     
     
         18 . The manufacturing method of a semiconductor device as claimed in  claim 16 , wherein the forming a via hole includes forming a resist mask on an upper interlayer insulation film formed to cover the dummy insulation films, the resist mask having a slit pattern extending vertically to the direction along which the layout pattern extends, and etching the upper interlayer insulation film and the interlayer insulation film with the use of the resist mask.