US2009256213A1PendingUtilityA1

Structure and method for manufacturing device with a v-shape channel nmosfet

Assignee: IBMPriority: Mar 25, 2008Filed: Jun 22, 2009Published: Oct 15, 2009
Est. expiryMar 25, 2028(~1.7 yrs left)· nominal 20-yr term from priority
H10D 64/01318H10D 84/856H10D 84/0181H10D 84/0177H10D 84/0167H10D 64/667H10D 64/027H10D 64/017H10D 62/292H10D 30/0225H10D 84/0195H10D 84/038
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Claims

Abstract

A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer.

Claims

exact text as granted — not AI-modified
1 . A device, comprising:
 a structure having an nMOSFET region;   a V-shape surface in the nMOSFET region, the V-shape surface having an orientation in a (100) plane and extending into a Si layer in the nMOSFET region;   a gate dielectric layer in the V-shape surface;   a metal gate layer on top of the gate dielectric layer; and   poly-Si on top of the metal gate layer.   
   
   
       2 . A device according to  claim 1 , wherein the gate dielectric layer is a high-k material. 
   
   
       3 . A device according to  claim 2 , wherein the high-k material is selected from the group consisting of: HfO2, ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3  and LaAlO 3 . 
   
   
       4 . A device according to  claim 2 , wherein the metal gate layer is selected from the group consisting of: TaN, TiN, TiAlN and WN. 
   
   
       5 . A device according to  claim 1 , wherein the poly-Si is in-situ doped with P. 
   
   
       6 . A device according to  claim 1 , wherein the V-shape surface has a depth less than the thickness of the Si layer.

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