Memory Data Transfer

Abstract

In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The second and third clock signals may have second and third frequencies, respectively, that are about equal to the first frequency. The second and third frequencies may be out of phase relative to each other. A controller may output a first data in response to a rising edge of the second clock signal and output a second data in response to another rising edge of the third clock signal.

1 . A method for controlling data output by a memory device, the method comprising:
 receiving, at a clock generator coupled to a controller, a first clock signal having a first frequency;   producing, at the clock generator, a second and third clock signals from the first clock signal, the second and third clock signals having second and third frequencies, respectively, that are substantially equal to the first frequency, the second and third clock signals being out of phase relative to each other; and   outputting, at the controller, a first data in response to a rising edge of the second clock signal and a second data in response to another rising edge of the third clock signal.   
     
     
         2 - 17 . (canceled)