NOR-Type Flash Memory Cell Array and Method for Manufacturing the Same

Abstract

Disclosed is a non-volatile (e.g., NOR type flash) memory cell array and a method for manufacturing the same. The memory cell array includes a plurality of isolation layers on a semiconductor substrate, parallel to a bit line and defining an active device area, a plurality of common source areas in the semiconductor substrate, separated from each other by the isolation layers such that the common source areas connect memory cells adjacent to each other in a bit line direction, a common source line on the semiconductor substrate, connected to each source area and extending in a word-line direction, an insulating spacer along a first sidewall of the common source line, a gate at a second sidewall of the insulating spacer including a tunnel oxide layer, a first electrode, an inter-electrode dielectric layer, and a second electrode, and a drain area in the semiconductor substrate on an opposite side of the gate from the common source area.

1 . A non-volatile memory cell array comprising:
 a plurality of isolation layers on a semiconductor substrate and parallel to a bit line, the isolation layers defining an active device area;   a plurality of common source areas in the semiconductor substrate and separated from each other by the isolation layers such that the common source areas connect two memory cells adjacent to each other in a bit line direction;   a common source line on the semiconductor substrate, connected to each source area and extending in a word-line direction;   an insulating spacer along a sidewall of the common source line;   a gate at a sidewall of the insulating spacer, comprising a tunnel oxide layer, a first electrode, an inter-electrode dielectric layer, and a second electrode; and   a drain area in the semiconductor substrate on an opposite side of the stack gate from the common source area.   
   
   
       2 . The cell array as claimed in  claim 1 , wherein the first electrode is separated from a memory cell adjacent to the first electrode in a word-line direction by the isolation layer. 
   
   
       3 . The cell array as claimed in  claim 1 , wherein the second electrode extends in a word-line direction and a sidewall of the second electrode self-aligned with a sidewall of the first electrode in a bit-line direction. 
   
   
       4 . The cell array as claimed in  claim 1 , wherein the insulating spacer electrically insulates the common source line from the gate. 
   
   
       5 . The cell array as claimed in  claim 1 , wherein the common source line and the second electrode include a same conductive material. 
   
   
       6 . The cell array as claimed in  claim 1 , wherein the second electrode has a spacer shape. 
   
   
       7 . The cell array as claimed in  claim 1 , wherein the semiconductor substrate includes a P-type dopant. 
   
   
       8 . The cell array as claimed in  claim 1 , wherein the inter-electrode dielectric layer comprises an oxide layer. 
   
   
       9 . The cell array as claimed in  claim 8 , wherein the inter-electrode dielectric layer consists essentially of the oxide layer. 
   
   
       10 . The cell array as claimed in  claim 1 , wherein the inter-electrode dielectric layer comprises an oxide-nitride-oxide dielectric layer. 
   
   
       11 . The cell array as claimed in  claim 1 , wherein the common source line comprises polysilicon. 
   
   
       12 . The cell array as claimed in  claim 11 , wherein the polysilicon is doped with at least one impurity. 
   
   
       13 . The cell array as claimed in  claim 1 , wherein the first electrode is a floating gate and the second electrode is a control gate. 
   
   
       14 . The cell array as claimed in  claim 1 , wherein the common source line comprises a conductive material having a height equal to a height of the second electrode. 
   
   
       15 . The cell array as claimed in  claim 1 , further comprising a first capping layer on upper parts of the second electrode and a second capping layer on an upper part of the common source line. 
   
   
       16 . The cell array as claimed in  claim 15 , further comprising a dielectric layer on the substrate. 
   
   
       17 . The cell array as claimed in  claim 16 , further comprising a drain contact in the dielectric layer, wherein the drain contact is connected to the drain area. 
   
   
       18 . The cell array as claimed in  claim 17 , further comprising a metal interconnection on the dielectric layer, wherein the metal interconnection is connected to the drain contact.