Fabrication management system

Abstract

With the evolution of technology, there is a continual demand for enhanced speed, capacity and efficiency. A modular, chip testing system associated with a single chip on a wafer is described. This system includes a performance structure for measuring chip performance during a testing period; a power structure for measuring chip power during the testing period; an interconnect structure for measuring characteristics of interconnects within the chip during the testing period; a device structure for measuring characteristics of devices within the chip during the testing period; and a plurality of probe pads coupled to the performance structure, power structure, interconnect structure, and the device structure, wherein the plurality of probe pads receive signals during the testing period that enable the modular, chip testing system to measure characteristics of the interconnects, characteristics of the devices, chip power, and chip performance.

1 . A modular, chip testing system associated with a single chip on a wafer, comprising:
 a performance structure for measuring chip performance during a testing period;   a power structure for measuring chip power during the testing period;   an interconnect structure for measuring characteristics of interconnects within the chip during the testing period;   a device structure for measuring characteristics of devices within the chip during the testing period; and   a plurality of probe pads coupled to the performance structure, power structure, interconnect structure, and the device structure,   wherein the plurality of probe pads receive signals during the testing period that enable the modular, chip testing system to measure characteristics of the interconnects, characteristics of the devices, chip power, and chip performance.   
   
   
       2 . The chip testing system of  claim 1 , wherein the testing period occurs before processing in the chip is complete. 
   
   
       3 . The chip testing system of  claim 1 , wherein measurements made during the testing period are selected from the group consisting of: transistor on-current, transistor off-current, threshold voltage, switching current, interconnect resistance, interconnect capacitances, operating speed, leakage power and dynamic power. 
   
   
       4 . The testing system of  claim 1 , wherein at least one of the performance structure, power structure, device structure, and interconnect structure comprises a ring oscillator representing a delay associated with a critical path in the chip.