Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root

Abstract

Systems, methods and computer program products for hardware assists for microcoded floating point divide and square root operations. Exemplary embodiments include a method including receiving a first microcoded instruction in the pipeline, decoding the first microcoded instruction in a decode stage of the pipeline, initiating a microcode engine coupled to the processor, with the microcode engine configured to process the streamlined microcode routine. During the delay between detecting the need to start a microcode routine and seeing the first microcode instruction actually issued, and using the processor cycle intended for the original instruction, hardware prepares for the microcode by pre-normalizing the operand, writing the pre-normalized operand to a scratch register coupled to the processor, conditionally generating a final result and discarding microcode routine instructions subsequent to the first microcode routine instruction and copying a final result from the scratch register to a floating point architectural register associated with the processor.

1 . A system for providing hardware assists for microcoded floating point divide and square root operations, the system consisting of:
 a processor;   a pipeline operatively coupled to the processor, wherein the processor is operative for:   receiving a first microcoded instruction in the pipeline;   decoding the first microcoded instruction in a decode stage of the pipeline;   flushing subsequent instructions already in the pipeline;   initiating a microcode engine coupled to the processor, the microcode engine configured to process the microcode routine;   for a 6-cycle period after receiving the microcoded instruction in the pipeline, performing in the instruction's pipeline slot of the pipeline:
 determining whether operands associated with the instruction are de-normalized; 
 in response to a determination that an operand associated with the microcode routine is de-normalized, pre-normalizing the operand; 
 writing the pre-normalized operand to a scratch register coupled to the processor; 
 in response to an operand being a normalized number, copying the operand into the scratch register; 
 determining whether operands associated with the instruction are a-typical and not dealt with by the streamlined microcode routine; 
   wherein the pipeline slot reserved for microcode instructions is used to perform processing selected from the group consisting of: (for divide); de-normalized divisor (implicit bit=0, ie fraction=0.XXX . . . X); either operand is an SNaN (Signaling Not a Number); either operand is a QNaN (Quiet Not a Number); normalized/0; 0/0; Inf/Inf; 0/X; X/Inf; Inf/X; (for square root); de-normalized operand; operand is an SNaN; operand is a QNaN; Sqrt(<0); Sqrt(−0); Sqrt(0); and Sqrt(Inf); and   producing a final result and copying the result from the scratch register to a floating point architectural register associated with the processor.