Single-Level Parallel-Gated Carry/Majority Circuits And Systems Therefrom

Abstract

A carry/majority circuit, comprising a plurality of differential transistor pairs coupled in parallel and forming a pair of output nodes, with a single parallel gated level. Current is steered through a leg of the transistor pair having a higher input voltage.

1 . The carry circuit further comprising a buffer circuit coupled to said output nodes to provide a full differential between said output nodes regardless of inputs to said differential transistor pairs. 
   
   
       2 . The carry circuit according to  claim 1 , wherein said buffer circuit is coupled to a clock. 
   
   
       3 . An accumulator architecture, comprising:
 a carry section wherein said carry section operates as a single-level parallel-gated logic;   a latch section coupled to said carry section; and   at least one clock coupled to latch section.   
   
   
       4 . The accumulator according to  claim 3 , wherein said carry section comprises a plurality of differential transistor pairs coupled in parallel. 
   
   
       5 . The accumulator according to  claim 3 , wherein said carry section comprises a plurality of single ended input transistors coupled in parallel. 
   
   
       6 . The accumulator according to  claim 3 , wherein said accumulator architecture is two gated levels. 
   
   
       7 . The accumulator according to  claim 3 , further comprising a buffer circuit coupled to said pair of output nodes. 
   
   
       8 . The accumulator according to  claim 3 , wherein said accumulator operates at a rate of at least 30 GHz. 
   
   
       9 . The accumulator according to  claim 3 , wherein said accumulator is fabricated by an indium phosphide (InP) heterojunction bipolar transistor (HBT) process. 
   
   
       10 . A direct digital synthesizer, comprising:
 a digital signal processor which generates a set of instructions;   an adder-accumulator that processes stored waveform data with said instructions and generates phase data, wherein said adder-accumulator includes a carry circuit having a single level parallel gated design with an integrated latch circuit;   a clock coupled to said adder-accumulator and said digital signal processor;   A phase to amplitude converter that processes said phase data that produces digitized waveform; and   a digital to analog converter that takes said digitized waveform and produces an analog synthesized output.   
   
   
       11 . The synthesizer according to  claim 10 , further comprising a filter coupled to said digital to analog converter and an amplifier coupled to said filter. 
   
   
       12 . The synthesizer according to  claim 10 , wherein said adder-accumulator further comprises a sum circuit with three series gated levels. 
   
   
       13 . The synthesizer according to  claim 10 , wherein said carry circuit comprises a plurality of differential transistor pairs.