US2009247249A1PendingUtilityA1
Data processing
Assignee: SONY COMPUTER ENTERTAINMENT INCPriority: Feb 21, 2006Filed: Feb 19, 2007Published: Oct 1, 2009
Est. expiryFeb 21, 2026(expired)· nominal 20-yr term from priority
G06F 9/455G06F 9/45504G06F 9/5066G06F 9/5077
44
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A data processor comprises a plurality of interconnected real processing units arranged to emulate the operation of an emulated processor having a plurality of interconnected emulated processing units. At least one emulated processing unit is emulated by contributions from two or more real processing units; and at least one real processing unit contributes to emulating two or more emulated processing units.
Claims
exact text as granted — not AI-modified1 . A data processor comprising a plurality of interconnected emulating processing units arranged to emulate the operation of an emulated processor having a plurality of interconnected emulated processing units, in which:
at least one emulated processing unit is emulated by contributions from two or more emulating processing units; and at least one emulating processing unit contributes to emulating two or more emulated processing units.
2 . A data processor according to claim 1 , in which the emulating processing units communicate with one another by a message-passing communication protocol.
3 . A data processor according to claim 2 , in which the emulating processing units are arranged to synchronise emulated operations via the message-passing communication protocol.
4 . A data processor according to claim 2 , in which the emulating processing units are interconnected by a circular data bus.
5 . A data processor according to claim 4 , in which the data bus is bidirectional.
6 . A data processor according to claim 1 , comprising a supervisory processor to interpret instructions relating to an emulated processor and provide information to the emulating processing units to allow the interpreted instructions to be executed.
7 . A data processor according to claim 6 , in which the information supplied to the emulating processing units comprises object code, native to the emulating processing units.
8 . A data processor according to claim 6 , in which the supervisory processor is operable to vary the allocation of emulation tasks to the emulating processing units, so as to change which emulated processing units are emulated by an emulating processing unit.
9 . A data processing method relating to a system having a plurality of interconnected emulating processing units arranged to emulate the operation of an emulated processor having a plurality of interconnected emulated processing units;
the method comprising the steps of: emulating an emulated processing unit by contributions from two or more emulating processing units; and emulating two or more emulated processing units by one emulating processing unit.
10 . Computer software for carrying out a method according to claim 9 .
11 . A medium by which computer software according to claim 10 is provided.
12 . A medium according to claim 11 , the medium being a storage medium.
13 . A medium according to claim 11 , the medium being a transmission medium.Join the waitlist — get patent alerts
Track US2009247249A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.