Method for forming interconnection levels of an integrated circuit

Abstract

A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure.

1 . A method for forming a stack of interconnection levels of an integrated circuit, comprising the steps of:
 (a) forming an interconnection level comprising conductive tracks formed above conductive vias, the tracks and the vias being laterally separated by a porous dielectric material;   (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings formed only above portions of porous dielectric material;   (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels of the stack, the conductive vias of an interconnection level of the stack having another interconnection level below contacting the conductive tracks of the interconnection level below; and   (d) annealing the structure.   
   
   
       2 . The method of  claim 1 , wherein an anneal step is performed before each repetition at step (c). 
   
   
       3 . The method of  claim 1 , wherein step (a) of formation of an interconnection level comprises the steps of:
 forming a layer of a porous dielectric material;   forming a silicon oxide layer, then a titanium nitride layer on the layer of porous dielectric material;   forming openings in the titanium nitride layer and in an upper portion of the oxide layer at the level of the desired conductive tracks;   forming, at the bottom of the openings, holes in the oxide layer and in an upper portion of the layer of porous dielectric material at the level of the desired conductive vias;   etching, outside the areas covered with the titanium nitride layer, until the bottom of the holes reaches the conductive tracks of the lower interconnection level;   forming a conductive material in the etched portion; and   removing the materials located above the layer of porous dielectric material.   
   
   
       4 . The method of  claim 3 , wherein the step of forming holes and the step of etching outside the areas covered by the titanium nitride layer are etch steps in the presence of argon and of C 4 F 8 . 
   
   
       5 . The method of  claim 3 , wherein the removal of the materials located above the layer of porous dielectric material is performed by chem./mech. polishing. 
   
   
       6 . The method of  claim 1 , wherein the layers of non porous insulating material are made of silicon-carbon nitride and the conductive tracks and the conductive vias are made of copper. 
   
   
       7 . An integrated circuit comprising a stack of interconnection levels, each interconnection level of the stack comprising conductive tracks and conductive vias, conductive tracks of different interconnection levels being adapted to be connected by the vias, the tracks and the vias of a same interconnection level being laterally separated by porous dielectric materials, non-porous insulating layers crossed by the vias being formed on each interconnection level, said non-porous insulating layers comprising openings located only on portions of porous dielectric materials. 
   
   
       8 . The integrated circuit of  claim 7 , wherein the porous dielectric materials have thicknesses ranging between 100 and 250 nm. 
   
   
       9 . The integrated circuit of  claim 7 , wherein the layers of non-porous insulating material are made of silicon-carbon nitride and the conductive tracks and the conductive vias are made of copper. 
   
   
       10 . The integrated circuit of  claim 7 , wherein the openings in the non-porous insulating layers have dimensions greater than 70 nm.