Source and body contact structure for trench-dmos devices using polysilicon

Abstract

A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed.

1 . A semiconductor device comprising:
 a P-body layer formed in an N-epitaxial layer;   a gate electrode formed in a trench in the P-body and N-epitaxial layers;   a top source region disposed on the P-body layer next to the gate electrode;   a gate oxide disposed between the gate electrode and the top source region, the P-body and the N-epitaxial layers;   a drain region formed by a substrate disposed below the bottom of the gate electrode and below the P-body layer   an oxide disposed on top of the source region and the gate electrode; and   a doped N+ polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide.   
   
   
       2 . The semiconductor device of  claim 1 , further comprising an exposed P+ Body contact region in an upper portion of the P-Body region, adjacent to the N+ polysilicon spacer. 
   
   
       3 . The semiconductor device of  claim 2 , wherein the exposed P+ body contact region has a top surface which is recessed below the bottom surface of the N+ source and spaced away from the N+ source by the N+ Polysilicon spacer. 
   
   
       4 . The semiconductor device of  claim 1  wherein the semiconductor device is an N-channel device. 
   
   
       5 . The semiconductor device of  claim 1  further comprising a barrier metal disposed on top of the doped N+ polysilicon spacer and the oxide. 
   
   
       6 . The semiconductor device of  claim 1  wherein the N+ polysilicon spacer is formed on a shelf on a portion of a top surface of the source region that is not covered by the oxide wherein the shelf is configured such that the N+ Polysilicon spacer contacts the top source region on a horizontal surface as well as a vertical surface. 
   
   
       7 . The semiconductor device of  claim 3  wherein a portion of a top surface of the P-body region not underlying the source region is recessed to a lower level than a portion of the top surface of the P-body region underlying the source region 
   
   
       8 . The semiconductor device of  claim 1  wherein a portion of a top surface of the P-body region not underlying the source region is recessed to a lower level than a portion of the top surface of the P-body region underlying the source region. 
   
   
       9 . The semiconductor device of  claim 1  wherein the N+ polysilicon spacer extends to a top portion of the source region. 
   
   
       10 . The semiconductor device of  claim 1  wherein the oxide is a reflowed oxide. 
   
   
       11 . The semiconductor device of  claim 1  further comprising Tungsten-plugs adjacent to the barrier metal and over the P-body region. 
   
   
       12 . The semiconductor device of  claim 1  wherein the top source region comprises N+ source. 
   
   
       13 . The semiconductor device of  claim 1  wherein the top source region comprises N− source. 
   
   
       14 . A method for manufacturing a semiconductor device comprising:
 a) providing an N-type epitaxial (N-epi) layer;   b) forming a trench mask on top of the N-epi layer;   c) etching the N-epi layer through the trench mask to a predetermined depth to form a trench;   d) forming a gate oxide on a bottom and sidewalls of the trench;   e) filling a remaining space in the trench with a conductive material to form a gate electrode;   f) removing the trench mask;   g) implanting and diffusing dopants into a top region of the N-epi layer to form a P-body layer;   h) implanting and diffusing dopants into a top region of the P-body layer to form a source region;   i) forming oxide on top of the gate electrode and the source region;   j) etching portions of the oxide to expose selected portions of the source region;   k) etching selected portions of the source region not covered by the oxide down to the p-body layer;   l) depositing N+ doped polysilicon on sidewalls of remaining portions of the source region and the oxide; and   m) etching back the N+ doped polysilicon to form an N+ doped polysilicon spacer disposed along the sidewalls of the remaining portions of the source region and the oxide.   
   
   
       15 . The method of  claim 14  wherein the conductive material is N+ doped polysilicon. 
   
   
       16 . The method of  claim 14  wherein c), d) and e) are implemented in a way that results in the conductive material of the gate electrode being recessed to below a surface of the N-epi layer. 
   
   
       17 . The method of  claim 14 , further comprising, after m) doping an exposed portions of the P-body layer P+ to form a body contact region proximate the polysilicon spacer. 
   
   
       18 . The method of  claim 14 , after step m, further comprising:
 depositing barrier metal over the P-body layer, N+ doped polysilicon spacer and the oxide;   depositing and patterning a metal on top of the barrier metal; and   depositing and patterning a passivation layer on top of the patterned metal.   
   
   
       19 . The method of  claim 14 , after step e, further comprising:
 etching back the conductive material filled in the trench to a level below a top surface of the N-epi layer.   
   
   
       20 . The method of  claim 14 , wherein step h) comprises implanting and diffusing dopants into the top region of the P-body layer to form an N+ source region. 
   
   
       21 . The method of  claim 14 , wherein step h) comprises implanting and diffusing dopants into the top region of the P-body layer to form an N− polysilicon source region. 
   
   
       22 . The method of  claim 14 , after step k) further comprising etching a portion of a top surface of the P-body region not covered by the oxide to a level below that of a bottom surface of the source region. 
   
   
       23 . A semiconductor device comprising:
 a body layer formed on an epitaxial layer, wherein the body layer and epitaxial layer are semiconductors of opposite polarity types;   a gate electrode formed in a trench in the body and epitaxial layers;   a top source region disposed on the body layer next to the gate electrode;   a gate oxide disposed between the gate electrode and the top source region, the body and the epitaxial layers;   a drain region formed by a substrate disposed below the bottom of the gate electrode and below the body layer;   an oxide disposed on top of the source region and the gate electrode; and   a doped N+ polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide.   
   
   
       24 . A method for manufacturing a semiconductor device comprising:
 a) providing an epitaxial layer of a first polarity type semiconductor;   b) forming a trench mask on top of the epitaxial layer;   c) etching the epitaxial layer through the trench mask to a predetermined depth to form a trench;   d) forming a gate oxide on a bottom and sidewalls of the trench;   e) filling a remaining space in the trench with a conductive material to form a gate electrode;   f) removing the trench mask;   g) implanting and diffusing dopants into a top region of of an opposite polarity type to that of the epitaxial layer into the epitaxial layer to form a body layer of an opposite polarity to that of the epitaxial layer;   h) implanting and diffusing dopants into a top region of the body layer to form a source region;   i) forming oxide on top of the gate electrode and the source region;   j) etching portions of the oxide to expose selected portions of the source region;   k) etching selected portions of the source region not covered by the oxide down to the body layer;   l) depositing doped polysilicon on sidewalls of remaining portions of the source region and the oxide; and   m) etching back the doped polysilicon to form a doped polysilicon spacer disposed along the sidewalls of the remaining portions of the source region and the oxide.