Structure and method for manufacturing device with a v-shape channel nmosfet

Abstract

A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer.

1 . A method of forming a device, comprising:
 forming an oxide layer on top of a CMOS structure having an nMOSFET region and a pMOSFET region in a (110) surface, wherein a top of the oxide layer is co-planar with a top of the pMOSFET region;   patterning a hardmask nitride to cover the oxide layer above the pMOSFET region;   removing poly-Si in the nMOSFET region;   removing gate oxide in the nMOSFET region to expose a Si layer in a channel area of the nMOSFET region;   removing Si to form a cavity in the channel area of the nMOSFET region;   performing selective Si epitaxial growth in the cavity to form a V-shape surface having an orientation in a (100) plane;   removing the hardmask nitride above the pMOSFET region;   depositing an nMOSFET gate dielectric layer;   depositing an nMOSFET metal gate layer, such that a top surface of the nMOSFET metal gate layer is below the top of the oxide layer;   depositing poly-Si on top of the nMOSFET metal gate layer, such that a top surface of the Poly-Si is below the top of the oxide layer;   removing a portion of the nMOSFET gate dielectric layer, such that a top surface of the nMOSFET gate dielectric layer is below the top surface of the oxide layer; and   removing the oxide layer.   
   
   
       2 . A method according to  claim 1 , wherein the forming the oxide layer step comprises performing a chemical mechanical polish (CMP) of the oxide layer. 
   
   
       3 . A method according to  claim 1 , wherein the removing the poly-Si step comprises performing a first reactive ion etching (RIE). 
   
   
       4 . A method according to  claim 1 , wherein the removing the gate oxide step comprises performing a second RIE. 
   
   
       5 . A method according to  claim 1 , wherein the removing the Si step comprises performing a third RIE. 
   
   
       6 . A method according to  claim 1 , wherein the nMOSFET gate dielectric layer is a high-k material. 
   
   
       7 . A method according to  claim 6 , wherein the high-k material is selected from the group consisting of: HfO2, ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3  and LaAlO 3 . 
   
   
       8 . A method according to  claim 1 , wherein the nMOSFET metal gate layer is selected from the group consisting of: TaN, TiN, TiAlN and WN. 
   
   
       9 . A method according to  claim 1 , wherein the poly-Si is in-situ doped with P. 
   
   
       10 . A method according to  claim 1 , wherein the removing a portion of the nMOSFET gate dielectric layer step comprises etching back the gate dielectric layer. 
   
   
       11 . A method according to  claim 1 , wherein the removing the oxide layer step comprises etching back the oxide layer. 
   
   
       12 . A method according to  claim 1 , wherein the cavity has a depth less than the thickness of the Si layer. 
   
   
       13 . A method of forming a device, comprising:
 depositing an oxide layer on top of a CMOS structure having an nMOSFET region and a pMOSFET region in a (110) surface;   performing a chemical mechanical polish (CMP) of the oxide layer;   patterning a hardmask nitride to cover the oxide layer above the pMOSFET region;   performing a first reactive ion etching (RIE) to remove poly-Si in the nMOSFET region;   performing a second RIE to remove gate oxide in the nMOSFET region and to expose a Si layer in a channel area of the nMOSFET region;   performing a third RIE to remove Si to form a cavity in the channel area of the nMOSFET region, wherein the cavity has a depth less than the thickness of the Si layer;   performing selective Si epitaxial growth in the cavity to form a V-shape surface having an orientation in a (100) plane;   removing the hardmask nitride above the pMOSFET region;   depositing an nMOSFET gate dielectric layer;   depositing an nMOSFET metal gate layer;   etching back a portion of the nMOSFET metal gate layer, such that a top surface of the nMOSFET metal gate layer is below the top of the oxide layer;   depositing in-situ doped poly-Si on top of the nMOSFET metal gate layer;   etching back a portion the in-situ doped poly-Si, such that a top surface of the in-situ doped poly-Si is below the top of the oxide layer;   etching back a portion of the nMOSFET gate dielectric layer, such that a top surface of the nMOSFET gate dielectric layer is below the top of the oxide layer; and   etching back the oxide layer.   
   
   
       14 . A method according to  claim 13 , wherein the nMOSFET gate dielectric layer is a high-k material. 
   
   
       15 . A method according to  claim 14 , wherein the high-k material is selected from the group consisting of: HfO2, ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3  and LaAlO 3 . 
   
   
       16 . A method according to  claim 13 , wherein the nMOSFET metal gate layer is selected from the group consisting of: TaN, TiN, TiAlN and WN. 
   
   
       17 . A device, comprising:
 a structure having an nMOSFET region;   a V-shape surface in the nMOSFET region, the V-shape surface having an orientation in a (100) plane and extending into a Si layer in the nMOSFET region;   a gate dielectric layer in the V-shape surface;   a metal gate layer on top of the gate dielectric layer; and   poly-Si on top of the metal gate layer.   
   
   
       18 . A device according to  claim 17 , wherein the gate dielectric layer is a high-k material. 
   
   
       19 . A device according to  claim 18 , wherein the high-k material is selected from the group consisting of: HfO2, ZrO 2 , Al 2 O 3 , TiO 2 , La 2 O 3 , SrTiO 3  and LaAlO 3 . 
   
   
       20 . A device according to  claim 18 , wherein the metal gate layer is selected from the group consisting of: TaN, TiN, TiAlN and WN. 
   
   
       21 . A device according to  claim 17 , wherein the poly-Si is in-situ doped with P. 
   
   
       22 . A device according to  claim 17 , wherein the V-shape surface has a depth less than the thickness of the Si layer.