Change in instruction behavior within code block based on program action external thereto

Abstract

Extended, alternate and/or modified instruction behavior can be established using a program construct that appears outside a bounded block of program code in such a way that the behavioral changes are limited to the bounded block and coincide with a particular point in the execution thereof. These extensions, alternations and/or modifications are supported in some processor embodiments in ways that add neither additional code space nor additional execution cycles to the bounded block. In general, the particular point in execution of the bounded block may be specified in a variety of ways, including positionally or temporally. Techniques described herein have broad applicability, but will be understood by persons of ordinary skill in the art in the context of certain illustrative code blocks, including zero- (or low-) overhead loops, lightweight procedures and very long instruction word (VLIW) type instruction packets, and processors that support them.

1 . A method comprising:
 establishing, for a particular execution context and using a program construct that appears outside a bounded block of program code, a behavioral extension whose effect is limited to the bounded block and which coincides with a particular point in the execution the bounded block,   wherein the behavioral extension codes a context switch but adds neither additional code space nor additional execution cycles to the bounded block.   
     
     
         2 . The method of  claim 1 ,
 wherein the bounded block includes a zero-overhead loop, and   wherein the behavioral extension includes a wait operation that coincides with the particular point in the execution the bounded block.   
     
     
         3 . The method of  claim 1 , further comprising:
 executing the program code on a processor that implements a switch on event multithreading (SOEMT) programming model, wherein the context switch coded by the behavioral extension is from the particular execution context to a next-highest priority active context of the executing program code.   
     
     
         4 . The method of  claim 1 ,
 wherein the program construct includes a wait offset instruction that precedes the bounded block in an execution sequence of the program code.   
     
     
         5 . The method of  claim 1 , further comprising:
 specifying the particular point using a positional indicator that identifies the particular point as coinciding with a particular instruction instance of the bounded block.   
     
     
         6 . The method of  claim 5 , wherein the specifying includes loading a register with a value indicative of one of:
 an instruction offset into the bounded block; and   a memory address.   
     
     
         7 . The method of  claim 1 , further comprising:
 specifying the particular point using a temporal indicator that identifies an execution cycle of the bounded block.   
     
     
         8 . The method of  claim 7 , wherein the specifying includes loading a register with a value indicative of one of:
 a cycle count; and   an instruction count.   
     
     
         9 . The method of  claim 1 , wherein the bounded block is one of:
 a low-overhead loop;   a lightweight procedure; and   a Very Long Instruction Word (VLIW) type instruction packet.   
     
     
         10 . The method of  claim 1 ,
 wherein limited extent of the bounded block allows all instructions thereof to reside entirely within a fetch buffer or cache line of a processor on which the program code is to be executed.   
     
     
         11 . The method of  claim 1 ,
 encoding the program code together with the program construct that establishes the behavioral extension in one or more computer readable media.   
     
     
         12 . An apparatus comprising:
 a processor including logic operable to establish a behavioral extension whose effect is limited to a bounded block of program code executing on the processor and which coincides with a particular point in the execution the bounded block, wherein the logic is triggered by execution on the processor of a program construct that appears outside the bounded block; and   a context controller responsive to the established behavioral extension.   
     
     
         13 . The apparatus of  claim 12 ,
 wherein neither the program construct nor the behavioral extension consumes either additional code space or additional execution cycles in the bounded block.   
     
     
         14 . The apparatus of  claim 12 ,
 wherein the processor implements switch on event multithreading (SOEMT);   wherein the bounded block includes a zero-overhead loop, and   wherein the behavioral extension includes a wait operation that coincides with the particular point in the execution the bounded block.   
     
     
         15 . The apparatus of  claim 12 ,
 wherein the program construct includes a wait offset instruction that precedes the bounded block in an execution sequence of the program code; and   wherein the wait offset instruction specifies the particular point either positionally or temporally.   
     
     
         16 . The apparatus of  claim 12 , further comprising:
 a register whose contents are specified upon execution of the program construct that appears outside the bounded block; and   a comparator of the logic responsive to a value in the register that coincides with the particular point in the execution the bounded block.   
     
     
         17 . A method comprising:
 establishing, using a program construct that appears outside a bounded block of program code, a behavioral extension whose effect is limited to the bounded block and which coincides with a particular point in the execution the bounded block,   wherein extent of the bounded block is architecturally-, rather than programmatically-, defined and wherein the behavioral extension adds neither additional code space nor additional execution cycles to the bounded block.   
     
     
         18 . The method of  claim 17 ,
 executing the program code on a processor that executes Very Long Instruction Word (VLIW) type instruction packets, wherein the architecturally-defined bounded block includes a VLIW type instruction packet.   
     
     
         19 . The method of  claim 17 ,
 wherein the architecturally-defined bounded block is sufficiently compact to reside entirely within a fetch buffer or individual cache line.   
     
     
         20 . The method of  claim 17 ,
 wherein the architecturally-defined bounded block is employed within a zero-overhead loop body.   
     
     
         21 . The method of  claim 17 ,
 wherein the behavioral extension includes a wait operation that coincides with the particular point in the execution the architecturally-defined bounded block.   
     
     
         22 . The method of  claim 17 ,
 wherein the program construct includes a wait offset instruction that precedes the architecturally-defined bounded block in an execution sequence of the program code.   
     
     
         23 . The method of  claim 17 , further comprising:
 specifying the particular point using one of:
 a positional indicator that identifies the particular point as coinciding with a particular instruction instance of the architecturally-defined bounded block; and 
 a temporal indicator that identifies an execution cycle of the architecturally-defined bounded block. 
   
     
     
         24 . The method of  claim 17 , wherein the behavioral extension includes one or more of:
 a wait function not coded within the architecturally-defined bounded block;   an acknowledge function not coded within the architecturally-defined bounded block; and   a trace enable function not coded within the architecturally-defined bounded block.   
     
     
         25 . The method of  claim 17 , further comprising:
 executing the program code on a processor that implements a switch on event multithreading (SOEMT) programming model.