Circuits to delay signals from a memory device

Abstract

Various embodiments include method and apparatus for receiving a clock signal, determining a number of delay elements based on a relationship between the clock signal and a delayed feedback signal generated based on the clock signal, calculating an amount of time corresponding to the number of delay elements, and delaying a control signal by the amount of time to generate an additional clock signal, the control signal having a frequency higher than a frequency of the clock signal. Other embodiments are described.

1 . A method comprising:
 receiving a clock signal;   determining a number of delay elements based on a relationship between the clock signal and a delayed feedback signal generated based on the clock signal;   calculating an amount of time corresponding to the number of delay elements; and   delaying a control signal by the amount of time to generate an additional clock signal, the control signal having a frequency higher than a frequency of the clock signal.   
   
   
       2 . The method of  claim 1  further comprising:
 receiving an input signal; and   multiplying a frequency of the input signal by a frequency ratio less than one to generate the clock signal such that the frequency of the clock signal is less than the frequency of the input signal.   
   
   
       3 . The method of  claim 1  further comprising:
 receiving an input signal; and   multiplying a frequency of the input signal by a frequency ratio greater than one to generate the clock signal such that the frequency of the clock signal is greater than the frequency of the input signal.   
   
   
       4 . The method of  claim 1  further comprising:
 controlling a reading of data from a memory device using the additional clock signal.   
   
   
       5 . The method of  claim 1 , wherein the frequency of the control signal is about two times the frequency of the clock signal. 
   
   
       6 . The method of  claim 1  further comprising:
 generating the clock signal based on an input signal that has a frequency equal to the frequency of the control signal.   
   
   
       7 . The method of  claim 1 , wherein determining the number of delay elements includes:
 delaying the clock signal to generate a feedback signal;   delaying the feedback signal to generate a delayed feedback signal; and   sampling the clock signal and the delayed feedback signal to determine the number of delay elements based on a phase difference between the clock signal and delayed feedback signal.   
   
   
       8 . A method comprising:
 receiving a first clock signal;   generating a second clock signal based on the first clock signal;   determining a number of delay elements corresponding to an amount of a period of the second clock signal;   calculating an amount of time corresponding to the number of delay elements;   receiving a control signal having a frequency higher than a frequency of the second clock signal; and   delaying the control signal by the amount of time corresponding to the number of delay elements.   
   
   
       9 . The method of  claim 8 , wherein the second clock signal is generated such that the frequency of the second clock signal is different from a frequency of the first clock signal. 
   
   
       10 . The method of  claim 9 , wherein a frequency of the first clock signal and the frequency of the control signal are equal. 
   
   
       11 . The method of  claim 10 , wherein the first clock signal and the control signal are received from a memory device. 
   
   
       12 . The method of  claim 11 , wherein the second clock signal is generated at a microcontroller. 
   
   
       13 . The method of  claim 8 , wherein the second clock signal is generated such that the frequency of the second clock signal is less than a frequency of the first clock signal. 
   
   
       14 . The method of  claim 8 , generating the second clock signal includes multiplying a frequency of the first clock signal by ratio to cause the frequency of the second clock signal to be less than the frequency of the first clock signal. 
   
   
       15 . The method of  claim 8 , wherein the second clock signal is generated such that the frequency of the second clock signal is one half of a frequency of the first clock signal. 
   
   
       16 . An apparatus comprising:
 a first circuit to receive a first clock signal to generate a second clock signal based on the first clock signal;   a second circuit including plurality of delay elements to delay the second clock signal with a number of delay element among the plurality of delay elements;   a third circuit to calculate an amount of time corresponding to the number of delay elements; and   a delay circuit to receive a control signal having a frequency higher than a frequency of the second signal and to delay the control signal by the amount of time corresponding to the number of delay elements.   
   
   
       17 . The apparatus of  claim 16 , wherein the first circuit includes a frequency modifier to modify a frequency of the first clock signal such that a frequency of the second clock signal is different from the frequency of the first clock signal. 
   
   
       18 . The apparatus of  claim 17 , wherein the frequency modifier includes a frequency multiple to multiply a frequency of the first clock signal by a ratio to generate the second clock signal. 
   
   
       19 . The apparatus of  claim 16 , wherein the third circuit includes a line to receive a signal to update the amount of time corresponding to the number of delay elements. 
   
   
       20 . The apparatus of  claim 16  further comprising a first device to provide the first clock signal and the control signal, wherein the first, second, and third circuits and the delay circuit are located at a second device separated from the first device.