Conductive structure of a chip and method for manufacturing the same

Abstract

A conductive structure of a chip and a method for manufacturing the conductive structure are provided. An under bump metal (UBM) is formed on the redistribution layer (RDL) by performing an electroless plating process. Subsequently, the solder bump is formed on the under bump metal for electrical connection. Thus, the photomask can be economized and the cost of manufacturing can be reduced.

1 . A conductive structure of a chip, comprising:
 a redistribution layer (RDL) formed on the chip, the redistribution layer having a first conductive area and a second conductive area, and electrically connecting to the chip through the first conductive area thereof;   an under bump metal (UBM) formed on the redistribution layer and electrically connecting to the redistribution layer through the second conductive area, wherein the UBM is an electroless plating layer; and   a bump formed on and electrically connecting to the UBM.   
   
   
       2 . The conductive structure as claimed in  claim 1 , wherein the chip is defined with an active surface and at least includes a pad being exposed on the active surface, the redistribution layer being formed on the active surface and electrically connected to the pad at the first conductive area thereof. 
   
   
       3 . The conductive structure as claimed in  claim 2 , wherein the electroless plating layer is made of Ni and Au. 
   
   
       4 . The conductive structure as claimed in  claim 3 , wherein the chip further comprises a first passivation layer which partially exposes the pad and forms the active surface with the pad. 
   
   
       5 . The conductive structure as claimed in  claim 4 , further comprising a second passivation layer overlaying the redistribution layer and partially exposing the second conductive area, wherein the electroless plating layer is electrically connected to the redistribution layer through the second conductive area thereof. 
   
   
       6 . The conductive structure as claimed in  claim 5 , wherein the electroless plating layer comprises an Ni layer and an Au layer, in which the Ni layer is formed on the second conductive area and the Au layer is formed on the Ni layer to electrically connect to the bump. 
   
   
       7 . The conductive structure as claimed in  claim 6 , wherein the redistribution layer is composed of a barrier layer and a conductive layer, in which the barrier layer overlays the first passivation layer and electrically connects to the pad and the conductive layer overlays the barrier layer. 
   
   
       8 . The conductive structure as claimed in  claim 7 , wherein the barrier layer is a Ti/W metal layer. 
   
   
       9 . The conductive structure as claimed in  claim 7 , wherein the conductive layer is made of one of Au, Cu, and Al. 
   
   
       10 . The conductive structure as claimed in  claim 2 , wherein the pad is made of one of Al and Cu. 
   
   
       11 . A method for manufacturing a conductive structure, comprising:
 forming a redistribution layer on a chip, wherein the redistribution layer has a first conductive area to electrically connect to the chip therethrough;   forming an under bump metal (UBM) by an electroless plating process to electrically connect to the redistribution layer through a second conductive area thereof; and   forming a bump electrically connecting to the UBM.   
   
   
       12 . The method as claimed in  claim 11 , wherein the step of forming a redistribution layer is forming the redistribution layer on a first passivation layer of the chip to electrically connect to a pad of the chip. 
   
   
       13 . The method as claimed in  claim 12 , further comprising a step after the step of forming the redistribution layer:
 partially exposing the redistribution layer at the second conductive area thereof.   
   
   
       14 . The method as claimed in  claim 13 , wherein the step of partially exposing the redistribution layer comprises:
 forming a second passivation layer overlaying the redistribution layer; and   patterning the second passivation layer to expose the second conductive area.   
   
   
       15 . The method as claimed in  claim 12 , wherein the step of forming a redistribution layer comprises:
 sputtering a barrier layer overlaying the first passivation layer and the pad;   sputtering a conductive layer on the barrier layer; and   patterning the barrier layer and the conductive layer.   
   
   
       16 . The method as claimed in  claim 15 , wherein the step of sputtering a barrier layer is sputtering a Ti/W metal layer, and the step of sputtering a conductive layer is sputtering one of Au, Al, and Cu. 
   
   
       17 . The method as claimed in  claim 16 , wherein the step of forming a bump is forming the bump to electrically connect to an Au layer of the UBM. 
   
   
       18 . The method as claimed in  claim 11 , wherein the step of forming a bump further comprises reflowing the bump. 
   
   
       19 . The method as claimed in  claim 11 , wherein the step of forming a UBM is forming an Ni layer and an Au layer, the Ni layer being formed at the second conductive area to electrically connect to the redistribution layer, and the Au layer being formed on the Ni layer.