Semiconductor device having fuse pattern and methods of fabricating the same

Abstract

A semiconductor device includes a semiconductor substrate having a fuse region and an interconnection region, a first insulating layer formed in the fuse region and the interconnection region, a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern, an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern, and a second insulating layer formed on the first insulating layer and covering the fuse pattern.

1 . A semiconductor device comprising:
 a semiconductor substrate having a fuse region and an interconnection region;   a first insulating layer formed in the fuse region and the interconnection region;   a plurality of fuse patterns formed on the first insulating layer in the fuse region, each fuse pattern including a first conductive pattern and a first capping pattern, and the fuse patterns having substantially uniform thicknesses;   an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse patterns; and   a second insulating layer formed on the first insulating layer and covering the fuse patterns.   
   
   
       2 . The semiconductor device according to  claim 1 , wherein the first and second capping patterns are anti-reflective layers. 
   
   
       3 . The semiconductor device according to  claim 1 , wherein each of the first and second conductive patterns further comprises one material layer selected from the group consisting of an aluminum layer, a tungsten layer, a copper layer and combinations thereof. 
   
   
       4 . The semiconductor device according to  claim 1 , wherein a thickness of the second capping pattern is equal to or greater than a thickness of at least one of the first capping patterns. 
   
   
       5 . The semiconductor device according to  claim 1 , wherein the first and second capping patterns are titanium nitride (TiN) layers. 
   
   
       6 . The semiconductor device according to  claim 1 , wherein each of the fuse patterns further comprises an interface pattern formed between the first conductive pattern and the first capping pattern. 
   
   
       7 . The semiconductor device according to  claim 1 , wherein the interconnection pattern further comprises an interface pattern interposed between the second conductive pattern and the second capping pattern. 
   
   
       8 . The semiconductor device according to  claim 1 , wherein:
 each of the fuse patterns further comprises a first barrier pattern formed between the first conductive pattern and the first insulating layer; and   the interconnection pattern further comprises a second barrier pattern formed between the second conductive pattern and the first insulating layer.   
   
   
       9 . The semiconductor device according to  claim 1 , wherein a bottom surface of each of the fuse patterns and a bottom surface of the interconnection pattern are substantially coplanar. 
   
   
       10 . The semiconductor device according to  claim 1 , further comprising a fuse window separated from at least one of the fuse patterns by the second insulating layer. 
   
   
       11 . The semiconductor device of  claim 1 , wherein the second insulating layer further comprises a surface overlapping at least one of the fuse patterns, the surface being substantially flat. 
   
   
       12 . A semiconductor device comprising:
 a semiconductor substrate having a fuse region and an interconnection region;   a first insulating layer formed in the fuse region and the interconnection region;   a fuse pattern formed on the first insulating layer in the fuse region, the fuse pattern including a first conductive pattern and a first capping pattern;   an interconnection pattern formed on the first insulating layer in the interconnection region, including a second conductive pattern and a second capping pattern, and having a thickness greater than the thickness of the fuse pattern;   a second insulating layer formed on the first insulating layer and covering the fuse pattern.   
   
   
       13 . The semiconductor device according to  claim 12 , further comprising a plurality of additional fuse patterns, the fuse pattern and the additional fuse patterns having substantially uniform thicknesses. 
   
   
       14 . The semiconductor device according to  claim 12 , further comprising a fuse window having a bottom surface separated from the fuse pattern by the second insulating layer.