Integration scheme for constrained seg growth on poly during raised s/d processing

Abstract

A method for constraining lateral growth of gate caps formed during an epitaxial silicon growth process to achieve raised source/drain regions on poly silicon is presented. The method is appropriate for integration into a manufacturing process for integrated circuit semiconductor devices. The method utilizes selective etch processes, dependant upon the material comprising the protective layer (hard mask) over the gate and the material of the spacers, e.g., oxide mask/nitride spacers, or nitride mask/oxide spacers.

1 . A device having a gate structure, the gate structure comprising:
 a first layer overlying a semiconductor substrate, the first layer comprising an upper-most surface relative the semiconductor substrate;   an epitaxial layer overlying the first layer, the epitaxial layer having an interface surface immediately adjacent to the upper-most surface of the first layer; and   a sidewall adjacent to the first layer and the epitaxial layer, the sidewall having an upper-most height relative to the semiconductor substrate.   
   
   
       2 . The device of  claim 1  wherein the gate structure comprises one or more layers including the first layer; a difference between the upper-most height of the sidewall and the upper-most surface of the first layer is a first dimension; and
 thickness of the epitaxial layer is a second dimension.   
   
   
       3 . The device of  claim 2 , wherein the second dimension is substantially the same as the first dimension. 
   
   
       4 . The device of  claim 2 , wherein the second dimension is less than the first dimension. 
   
   
       5 . The device of  claim 2 , wherein the second dimension is greater than the first dimension. 
   
   
       6 . The device of  claim 1 , wherein the first layer comprises a doped source drain area, and the epitaxial layer is a substantially undoped epitaxial layer. 
   
   
       7 . The device of  claim 1 , wherein the first layer comprises a doped source drain area, and the epitaxial layer is a doped epitaxial layer. 
   
   
       8 . The device of  claim 1 , wherein the sidewalls comprise an oxide. 
   
   
       9 . The device of  claim 1 , wherein the sidewalls comprise a nitride. 
   
   
       10 . The device of  claim 1 , wherein the gate stack comprises polysilicon. 
   
   
       11 . The device of  claim 1 , wherein the semiconductor substrate is a portion of a semiconductor on insulator (SOI) substrate. 
   
   
       12 . A device comprising:
 a gate structure comprising a first layer overlying an active silicon region;   an epitaxial layer overlying the active silicon region and overlying the first layer, the epitaxial layer having an interface surface and an upper surface, the interface surface being immediately adjacent to the first layer, and the upper surface being substantially parallel to the interface surface.   
   
   
       13 . The device of  claim 12 , wherein the semiconductor substrate is a portion of a semiconductor on insulator (SOI) substrate. 
   
   
       14 . The device of  claim 12  further comprising a sidewall adjacent the gate structure. 
   
   
       15 . The device of  claim 14 , wherein the sidewall comprises an oxide. 
   
   
       16 . The device of  claim 14 , wherein the sidewall comprises a nitride. 
   
   
       17 . The device of  claim 14  wherein a dimension between the active silicon region and an upper-most surface of the gate structure is greater than an upper-most dimension of the sidewall. 
   
   
       18 . The device of  claim 14  wherein a dimension between the active silicon region and an upper-most surface of the gate structure is less than an upper-most dimension of the sidewall. 
   
   
       19 . The device of  claim 18 , wherein the semiconductor substrate is a portion of a semiconductor on insulator (SOI) substrate. 
   
   
       20 . The device of  claim 14  wherein a dimension between the active silicon region and an upper-most surface of the gate structure is the same as an upper-most dimension of the sidewall.