Semiconductor devices having a convex active region

Abstract

Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

1 . A semiconductor device comprising:
 a semiconductor substrate comprising a cell array region;   cell device isolation patterns in the cell array region that define cell active regions having a convex upper surface; and   cell gate patterns crossing over the convex upper surfaces of the cell active regions and over the cell device isolation patterns.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the convex upper surfaces have a radius of curvature that is about 1/10 to about ½ of a width thereof, and wherein a top surface of the cell device isolation pattern is lower than the convex upper surfaces. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the semiconductor substrate further comprises a peripheral circuit region and wherein the device further comprises:
 peripheral device isolation patterns in the peripheral circuit region that define peripheral active regions; and   a peripheral gate pattern on the peripheral active regions, wherein the peripheral gate patterns comprise a stacked peripheral gate insulating layer and peripheral gate conductive layer and wherein the cell gate patterns comprise a stacked tunnel insulating layer, charge storage layer, blocking dielectric layer and cell gate electrode layer.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the peripheral gate conductive layer comprises a polysilicon layer, the cell gate electrode layer comprises a metal nitride, the charge storage layer comprises an oxide and/or nitride of silicon, metal and/or metal silicide, and the blocking insulating layer comprises an insulating material having a higher dielectric constant than a dielectric constant of the charge storage layer. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the charge storage layer comprises a silicon nitride layer, the blocking dielectric layer comprises an aluminum oxide layer, and the cell gate electrode layer comprises a tantalum nitride layer. 
     
     
         6 . The semiconductor device of  claim 3 , wherein a height of a top surface of the peripheral device isolation pattern is no less than a height of a top surface of the peripheral active region. 
     
     
         7 . The semiconductor device of  claim 3 , wherein a first portion of the peripheral gate pattern comprises a low voltage transistor, and a second portion of the peripheral gate pattern comprises a high voltage transistor, wherein the peripheral gate insulating layer of the peripheral gate pattern comprising the high voltage transistor is thicker than the peripheral gate insulating layer of the peripheral gate pattern comprising the low voltage transistor. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising hemispherical silicon grains between the cell active regions and the cell gate patterns, the hemispherical silicon grains extending from the semiconductor substrate.