Multi-Thread Peripheral Processing Using Dedicated Peripheral Bus

Abstract

One embodiment of the present invention performs peripheral operations in a multi-thread processor. A peripheral bus is coupled to a peripheral unit to transfer peripheral information including a command message specifying a peripheral operation. A processing slice is coupled to the peripheral bus to execute a plurality of threads. The plurality of threads includes a first thread sending the command message to the peripheral unit.

1 . An apparatus comprising:
 an instruction resource configured to perform an operation other than a peripheral operation, the operation specified in a first instruction dispatched from a first of a plurality of threads; and   a peripheral unit interface configured to send a command message specifying a peripheral operation to a peripheral unit over a peripheral bus responsive to a second instruction dispatched from a second of the plurality of threads;   wherein the instruction resource and the peripheral unit interface are configured to execute the first and second instructions concurrently during a same clock cycle.   
   
   
       2 . The apparatus of  claim 1 , further comprising:
 a plurality of program counters, wherein each of the plurality of threads corresponds to one of the program counters.   
   
   
       3 . The apparatus of  claim 2 , further comprising:
 a plurality of program base registers, each program base register corresponding to one of the program counters and to one of the threads and configured to provide a third instruction dispatched from a third of the plurality of threads that is fetched from a location corresponding to the sum of:   the contents of the program counter corresponding to the third of the plurality of threads, and   the contents of the program base register corresponding to the third of the plurality of threads.   
   
   
       4 . The apparatus of  claim 3 , wherein the third instruction comprises a local transfer branch target within an instruction space for the third of the plurality of threads. 
   
   
       5 . The apparatus of  claim 2 , further comprising:
 a plurality of data base registers, each data base register corresponding to one of the program counters and to one of the threads and configured to provide a third instruction dispatched from a third of the plurality of threads that operates on data from a location corresponding to the sum of:
 the contents of the program counter corresponding to the third of the plurality of threads, and 
 the contents of the data base register corresponding to the third of the plurality of threads. 
   
   
   
       6 . The apparatus of  claim 5 , wherein the location is within a data space for the third of the plurality of threads. 
   
   
       7 . A method comprising:
 performing an operation other than a peripheral operation, the operation specified in a first instruction dispatched from a first of a plurality of threads; and   sending a command message specifying a peripheral operation to a peripheral unit over a peripheral bus responsive to a second instruction dispatched from a second of the plurality of threads;   wherein the first and second instructions are executed concurrently during a same clock cycle.   
   
   
       8 . The method of  claim 7 , wherein each of the plurality of threads corresponds to one of a plurality of program counters. 
   
   
       9 . The method of  claim 8 , wherein each of a plurality of program base registers corresponds to one of the program counters and to one of the threads, the method further comprising:
 fetching a third instruction from a third of the plurality of threads from a location corresponding to the sum of:
 the contents of the program counter corresponding to the third of the plurality of threads, and 
 the contents of the program base register corresponding to the third of the plurality of threads. 
   
   
   
       10 . The method of  claim 9 , wherein the third instruction comprises a local transfer branch target within an instruction space for the third of the plurality of threads. 
   
   
       11 . The method of  claim 8 , wherein each of a plurality of data base registers corresponds to one of the program counters and to one of the threads, the method further comprising:
 fetching a third instruction dispatched from a third of the plurality of threads, where the third instruction operates on data from a location corresponding to the sum of:
 the contents of the program counter corresponding to the third of the plurality of threads, and 
 the contents of the data base register corresponding to the third of the plurality of threads. 
   
   
   
       12 . The method of  claim 11 , wherein the location is within a data space for the third of the plurality of threads. 
   
   
       13 . An apparatus comprising:
 a plurality of program counters;   a plurality of program base registers, each program base register corresponding to a program counter and to a thread; and   an instruction processing unit to process instructions fetched from a program memory, wherein each instruction corresponds to a thread, the instruction for the corresponding thread fetched from a location corresponding to the sum of the contents of the program counter corresponding to the thread and the contents of the program base register corresponding to the thread.   
   
   
       14 . The apparatus of  claim 13 , wherein the location comprises a local transfer branch target within an instruction space for the thread. 
   
   
       15 . An apparatus comprising:
 a plurality of program counters;   a plurality of data base registers, each data base register corresponding to a program counter and to a thread; and   an instruction processing unit to process instructions fetched from a program memory, wherein each instruction corresponds to a thread, the instruction for the corresponding thread operating on data from a location corresponding to the sum of the contents of the program counter corresponding to the thread and the contents of the data base register corresponding to the thread.   
   
   
       16 . The apparatus of  claim 15 , wherein the location is within a data space for the thread.