Flash memory devices comprising pillar patterns and methods of fabricating the same

Abstract

Flash memory devices include pillar patterns formed between selected pairs of floating gates and control gate extensions that penetrate between selected pairs of floating gates are provided. Methods of fabricating the flash memory devices are also provided.

1 . A method of fabricating a flash memory device, comprising:
 forming a plurality of parallel trench mask patterns on a semiconductor substrate;   etching the semiconductor substrate using the trench mask patterns as etch masks to form a trench region defining a plurality of parallel active regions;   forming an isolation layer and a pillar filling the trench region, wherein sidewalls and a bottom surface of the pillar are covered by the isolation layer;   removing the trench mask patterns to form grooves exposing the active regions;   forming insulated floating gate patterns filling the grooves;   selectively etching the pillar to form recessed regions between the floating gate patterns;   sequentially forming an inter-gate dielectric layer and a control gate conductive layer on the semiconductor substrate having the recessed regions; and   continuously patterning the control gate conductive layer, the inter-gate dielectric layer, and the floating gate patterns to form floating gates interposed between control gate electrodes and the active regions as well as the plurality of control gate electrodes crossing over the active regions,   wherein each of the control gate electrodes has control gate extensions which penetrate between the floating gates.   
   
   
       2 . The method according to  claim 1 , wherein each of the trench mask patterns is formed by sequentially stacking at least a buffer layer pattern and a chemical mechanical polishing (CMP) stop pattern. 
   
   
       3 . The method according to  claim 2 , wherein the buffer layer pattern is formed of a silicon oxide layer, and the CMP stop pattern is formed of a polysilicon layer. 
   
   
       4 . The method according to  claim 2 , further comprising forming a hard mask pattern on the CMP stop pattern. 
   
   
       5 . The method according to  claim 2 , wherein forming the isolation layer and the pillar includes:
 forming an insulating layer surrounding the trench mask patterns and covering an inner wall of the trench region;   forming a pillar layer completely filling the trench region and covering an entire surface of the semiconductor substrate; and   planarizing the pillar layer and the insulating layer until a top surface of the CMP stop pattern is exposed.   
   
   
       6 . The method according to  claim 1 , wherein the pillar is formed of a material layer having an etch selectivity with respect to the isolation layer. 
   
   
       7 . The method according to  claim 1 , wherein the pillar is formed of a silicon nitride layer. 
   
   
       8 . The method according to  claim 1 , wherein a lower region of the pillar is lower than top surfaces of the active regions. 
   
   
       9 . The method according to  claim 2 , wherein forming the grooves includes:
 selectively removing the CMP stop pattern to expose the buffer layer pattern; and   isotropically etching the buffer layer pattern and the isolation layer to expose the active regions.   
   
   
       10 . The method according to  claim 1 , wherein forming the insulated floating gate patterns includes:
 forming a tunneling dielectric layer on the exposed active regions;   forming a floating gate conductive layer filling the grooves on the semiconductor substrate having the tunneling dielectric layer; and   planarizing the floating gate conductive layer until a top surface of the pillar is exposed.   
   
   
       11 . The method according to  claim 1 , wherein forming the recessed regions between the floating gate patterns includes selectively etching the pillar using a wet etching process to form pillar patterns lower than bottom surfaces of the floating gate patterns. 
   
   
       12 . The method according to  claim 1 , wherein forming the recessed regions between the floating gate patterns includes completely removing the pillar using a wet etching process. 
   
   
       13 . The method according to  claim 1 , wherein lower regions of the control gate extensions are lower than bottom surfaces of the floating gates.