Method of fabricating a semiconductor device

Abstract

Embodiments relate to a method of fabricating a semiconductor device. In embodiments, a gate pattern may be formed on a semiconductor substrate, and sidewalls having a lower height than a height of the gate pattern may be formed at both sides of the gate pattern using a photoresist pattern. A silicide layer may be formed on exposed upper surface and side surfaces of the gate pattern and a portion of the semiconductor substrate at both sides of the sidewalls. Therefore, the silicide layer formed on a gate may be enlarged, and may reduce gate resistance.

1 - 20 . (canceled) 
   
   
       21 . A device, comprising:
 a semiconductor substrate;   a gate electrode formed over the semiconductor substrate;   an oxide layer having a height lower than a height of the gate electrode at sides of the gate electrode;   a sidewall formed over the oxide layer; and   a silicide layer covering a top surface of the gate electrode and a portion of a side surface of the gate electrode,   wherein a width of the combined silicide layer is greater than a width of the gate electrode.   
   
   
       22 . The device of  claim 21 , wherein the silicide layer further covers the semiconductor substrate. 
   
   
       23 . The device of  claim 21 , wherein the silicide layer covers the top surface of the gate electrode and a top surface of the oxide layer to form a combined silicide layer. 
   
   
       24 . The device of  claim 21 , wherein the oxide layer comprises a poly oxide layer and a cap oxide layer. 
   
   
       25 . A device comprising:
 a gate electrode having first height formed on a semiconductor substrate;   sidewalls having a second height formed on the semiconductor substrate adjacent to the gate;   a silicide layer formed on a top surface of the gate electrode and at least a portion of a top surface of the sidewalls,   wherein the silicide layer is formed on the oxide layer adjacent to the sidewalls and on a side portion of the gate electrode,   wherein the silicide layer over the gate electrode and over the oxide layer forms a single surface having a width greater than a width of the gate electrode.   
   
   
       26 . The device of  claim 25 , wherein the sidewalls comprise an oxide layer formed directly adjacent to the sidewalls and over a portion of the semiconductor substrate, and a nitride layer formed over the oxide layer.