Circuit and methods for eliminating skew between signals in semicoductor integrated circuit

Abstract

A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller includes an edge information storage unit which stores edge information output from the semiconductor memory device, a pseudo data pattern generating unit which outputs pseudo data including a pattern similar to actually transmitted data, a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result, and a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.

1 . A circuit for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller, the circuit comprising:
 an edge information storage unit which stores edge information output from the semiconductor memory device;   a pseudo data pattern generating unit which outputs pseudo data including a pattern corresponding to actually transmitted data;   a phase detecting unit which receives the edge information from the edge information storage unit and the pseudo data from the pseudo data pattern generating unit to detect a phase difference between the data and the clock signal and generate a corresponding detection result; and   a phase control unit which controls a phase of the clock signal according to the corresponding detection result from the phase detecting unit, so as to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.   
   
   
       2 . The circuit according to  claim 1 , wherein the circuit performs a clock data recovery (CDR) operation which extracts a sampling clock from the data in the data read operation of the semiconductor memory device so as to eliminate the skew. 
   
   
       3 . The circuit according to  claim 2 , wherein the circuit performs a per-data input/output pin skew elimination operation in each refresh section of the semiconductor memory device to reduce a dynamic skew. 
   
   
       4 . The circuit according to  claim 3 , wherein the dynamic skew is caused by a variation in operation temperature and voltage. 
   
   
       5 . The circuit according to  claim 4 , wherein the refresh section is a CAS (Column Address Strobe) before RAS (Row address strobe) (CBR) section of the semiconductor memory device. 
   
   
       6 . A method for eliminating a skew between data and a clock signal in an interface between a semiconductor memory device and a memory controller, the method comprising:
 reading data edge information from the semiconductor memory device;   detecting a phase difference between the data and the clock signal using the read data edge information and preset data information; and   adjusting a phase of the clock signal according to the detected phase difference, wherein clock data recovery operation is performed in each data period to eliminate a per-data input/output pin skew in a data write and read operation of the semiconductor memory device.   
   
   
       7 . The method according to  claim 6 , wherein in the data read operation of the semiconductor memory device, clock data recovery operation for extracting a sampling clock from the data is performed so as to eliminate the skew. 
   
   
       8 . The method according to  claim 6 , further comprising eliminating a dynamic skew caused by variation in operation temperature and voltage. 
   
   
       9 . The method according to  claim 8 , wherein the dynamic skew is eliminated in a refresh section of the semiconductor memory device.