Erasing control circuit and method for erasing environment configuration memory in a computer system

Abstract

A computer system includes a power switch, a reset switch, environment configuration memory, and an erasing control circuit. The power switch is for starting the computer system as triggered. The reset switch is for resetting the computer system as triggered. The environment configuration memory is for storing an operational environment setting of the computer system. The environment configuration memory has a power supply pin. The erasing control circuit is connected to the power switch, the reset switch and the power supply pin. The erasing control circuit connects the power supply pin to a ground voltage as the power switch and the reset switch are triggered simultaneously.

1 . A computer system, comprising:
 a power switch, for switching the computer system on when the power switch triggered;   a reset switch, for resetting the computer system when the reset switch triggered;   an environment configuration memory, for storing an operational environment setting; and   an erasing control circuit, connected to the power switch, the reset switch and the environment configuration memory, wherein the erasing control circuit erases the operational environment setting of the environment configuration memory when the power switch and the reset switch triggered simultaneously.   
   
   
       2 . The computer system according to  claim 1 , wherein the erasing control circuit comprises a power supply pin, and the erasing control circuit connects the power supply pin to a ground voltage to erase the operational environment setting of the environment configuration memory when the power switch and the reset switch triggered simultaneously. 
   
   
       3 . The computer system according to  claim 2 , further comprising:
 a power supply circuit, for supplying a power to the environment configuration memory, wherein the power supply circuit comprises:
 an input terminal, for receiving a positive voltage; 
 a first output terminal, wherein the power supply circuit selectively outputs the positive voltage at the first output terminal by a jump; and 
 a second output terminal, for outputting the positive voltage. 
   
   
   
       4 . The computer system according to  claim 3 , wherein the erasing control circuit comprises:
 a first switch, having one end connected to the first output terminal of the power supply circuit and anther end connected to the power supply pin, wherein a control terminal of the first switch is connected to a node, and the node is connected to the second output terminal of the power supply circuit;   a second switch, having one end connected to the power supply pin, and another end connected to a first constant voltage, wherein a control terminal of the second switch is connected to the node;   a third switch, having one end connected to the node, and another end connected to a second constant voltage, wherein a control terminal of the third switch is connected to the power switch;   a fourth switch, having one end connected to the node, and another end connected to a third constant voltage, wherein a control terminal of the fourth switch is connected to the reset switch; and   a voltage lifting circuit, connected to the control terminal of the third switch and the control terminal of the fourth switch, for turning on the third switch and the fourth switch as the power switch and the reset switch are not triggered.   
   
   
       5 . The computer system according to  claim 4 , wherein the voltage lifting circuit comprises:
 a fifth switch, having one end connected to the second output terminal of the power supply circuit and another end connected to the control terminal of the third switch via a first resistor, wherein a control terminal of the fifth switch receives the positive voltage;   a sixth switch, having one end connected to the second output terminal of the power supply circuit, and another end connected to the control terminal of the fourth switch via a second resistor, wherein a control terminal of the sixth switch receives the positive voltage;   a third resistor, having one end connected to the second output terminal of the power supply circuit, and the end connected to the control terminal of the third switch; and   a fourth resistor, having one end connected to the second output terminal of the power supply circuit, and the other end connected to the control terminal of the fourth switch.   
   
   
       6 . The computer system according to  claim 5 , wherein the first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch respectively comprise at least a metal oxide semiconductor (MOS) transistor. 
   
   
       7 . The computer system according to  claim 1 , wherein the environment configuration memory is a complementary metal oxide semiconductor (CMOS) random-access memory (RAM). 
   
   
       8 . The computer system according to  claim 1 , wherein the operational environment setting is a basic input/output system (BIOS) setting. 
   
   
       9 . An erasing control circuit of a computer system, the computer system having a power switch, a reset switch, and an environment configuration memory, the power switch switching the computer system on when the power switch triggered, the reset switch resetting the computer system when the reset switch triggered, the environment configuration memory storing an operational environment setting, the erasing control circuit comprising:
 a first switch, having one end connected to the first output terminal of the power supply circuit and another end connected to the environment configuration memory, wherein a control terminal of the first switch is connected to a node, and the node is connected to the second output terminal of the power supply circuit;   a second switch, having one end connected to the environment configuration memory, and another end connected to a first constant voltage, wherein a control terminal of the second switch is connected to the node;   a third switch, having one end connected to the node, and another end connected to a second constant voltage, wherein a control terminal of the third switch is connected to the power switch;   a fourth switch, having one end connected to the node, and another end connected to a third constant voltage, wherein a control terminal of the fourth switch is connected to the reset switch; and   a voltage lifting circuit, connected to the control terminal of the third switch and the control terminal of the fourth switch, for turning on the third switch and the fourth switch as the power switch and the reset switch are not triggered.   wherein when the power switch and the reset switch are triggered simultaneously, the erasing control circuit erases the operational environment setting of the environment configuration memory.   
   
   
       10 . The erasing control circuit according to  claim 9 , wherein the environment configuration memory comprises a power supply pin, and the first switch and the second switch are connected to the power supply pin of the environment configuration memory. 
   
   
       11 . The erasing control circuit according to  claim 9 , wherein the voltage lifting circuit comprises:
 a fifth switch, having one end connected to the second output terminal of the power supply circuit and another end connected to the control terminal of the third switch via a first resistor, wherein a control terminal of the fifth switch receives the positive voltage;   a sixth switch, having one end connected to the second output terminal of the power supply circuit, and another end connected to the control terminal of the fourth switch via a second resistor, wherein a control terminal of the sixth switch receives the positive voltage;   a third resistor, having one end connected to the second output terminal of the power supply circuit, and the end connected to the control terminal of the third switch; and   a fourth resistor, having one end connected to the second output terminal of the power supply circuit, and the other end connected to the control terminal of the fourth switch.   
   
   
       12 . The erasing control circuit according to  claim 11 , wherein the first switch, the second switch, the third switch, the fourth switch, the fifth switch, the sixth switch respectively comprise at least a MOS transistor. 
   
   
       13 . The erasing control circuit according to  claim 9 , wherein the operational environment setting is a BIOS setting. 
   
   
       14 . A method for erasing environment configuration memory of a computer system, the computer system having a power switch and a reset switch, the method comprising:
 storing an operational environment setting in the environment configuration memory; and   erasing the operational environment setting of the environment configuration memory as the power switch and the reset switch are triggered simultaneously.   
   
   
       15 . The method according to  claim 14 , wherein the operational environment setting is a BIOS setting.