Multi-state memory cell

Abstract

Floating-gate memory cells having a split floating gate facilitate decreased sensitivity to localized defects in the tunnel dielectric and/or the intergate dielectric. Such memory cells also permit storage of more than one bit per cell. Methods of the various embodiments facilitate fabrication of floating gate segments having dimensions less than the capabilities of the lithographic processed used to form the gate stacks.

1 . A floating-gate memory cell, comprising:
 a tunnel dielectric over a semiconductor;   two or more segments of a floating gate over the tunnel dielectric, wherein the segments of the floating gate are separated from each other;   an intergate dielectric over the floating gate;   a control gate over the intergate dielectric; and   source/drain regions formed in the semiconductor adjacent the tunnel dielectric.   
   
   
       2 . The floating-gate memory cell of  claim 1 , wherein the floating gate comprises two or more segments of material capable of holding a charge. 
   
   
       3 . The floating-gate memory cell of  claim 2 , wherein the material capable of holding a charge is a polysilicon material. 
   
   
       4 . The floating-gate memory cell of  claim 1 , wherein at least a portion of the intergate dielectric is adjacent the tunnel dielectric. 
   
   
       5 . The floating-gate memory cell of  claim 4 , wherein at least a portion of the intergate dielectric adjacent the tunnel dielectric is interposed between two segments of the floating gate. 
   
   
       6 . A floating-gate memory cell, comprising:
 a tunnel dielectric over a semiconductor;   a floating gate over the tunnel dielectric, wherein the floating gate is split into two or more discrete segments capable of holding a charge;   an intergate dielectric over the floating gate;   a control gate over the intergate dielectric; and   source/drain regions formed in the semiconductor adjacent the tunnel dielectric.   
   
   
       7 . A floating-gate memory cell, comprising:
 a tunnel dielectric over a semiconductor;   two or more segments of a floating gate formed on the tunnel dielectric;   an intergate dielectric formed on the floating gate, wherein at least a portion of the intergate dielectric is formed on the tunnel dielectric;   a control gate over the intergate dielectric; and   source/drain regions formed in the semiconductor adjacent the tunnel dielectric.   
   
   
       8 . A memory cell comprising:
 a tunnel dielectric over a semiconductor;   two or more charge-storage segments over at least a portion of the tunnel dielectric, wherein the segments are separated from each other and wherein portions of a charge storage material are etched to form the charge-storage segments;   an intergate dielectric over the charge-storage segments; and   a control gate over the intergate dielectric.   
   
   
       9 . The memory cell of  claim 8 , wherein the memory cell is written by:
 establishing a programming field between the control gate and a first source/drain region of the memory cell; and   storing charge in a first charge-storage segment of the two or more charge-storage segments without materially affecting a charge level of a second charge-storage segment of the two or more charge-storage segments;   wherein the first charge-storage segment of the two or more charge-storage segments is adjacent the first source/drain region of the memory cell and the second charge-storage segment of the two or more charge-storage segments is adjacent a second source/drain region of the memory cell.   
   
   
       10 . The memory cell of  claim 9 , wherein establishing a programming field further comprises floating the second source/drain region. 
   
   
       11 . The memory cell of  claim 9 , wherein at least one additional charge-storage segment is interposed between the first and second charge-storage segments. 
   
   
       12 . The memory cell of  claim 9 , wherein establishing a programming field further comprises applying a first potential to the control gate and applying a second potential to the first source/drain region, the second potential being lower than the first potential. 
   
   
       13 . The memory cell of  claim 9 , further comprising:
 establishing a programming field between the control gate and the second source/drain region of the memory cell; and   storing charge in the second charge-storage segment of the two or more charge-storage segments without materially affecting a charge level of the first charge-storage segment of the two or more charge-storage segments.   
   
   
       14 . The memory cell of  claim 8 , wherein a portion of the integrate dielectric is on the tunnel dielectric between adjacent charge-storage segments. 
   
   
       15 . The memory cell of  claim 8 , wherein the integrate dielectric is oxide-nitride-oxide. 
   
   
       16 . The memory cell of  claim 8 , wherein the two or more charge-storage segments are polysilicon. 
   
   
       17 . The memory cell of  claim 8 , wherein the charge storage material is formed over the tunnel dielectric and one or more support structures on the tunnel dielectric. 
   
   
       18 . The memory cell of  claim 17 , wherein the etched portions of the charge storage material that are etched to form the segments are removed by the etching to expose portions of the tunnel dielectric and to expose an upper surface of the one or more support structures, wherein the etching leaves the charge-storage segments on sidewalls of the one or more support structures. 
   
   
       19 . The memory cell of  claim 18 , wherein the one or more support structures are removed so as to leave the charge-storage segments free standing. 
   
   
       20 . The memory cell of  claim 18 , wherein a width of the one or more support structures is reduced prior to forming the charge storage material thereover.