Semiconductor device

Abstract

An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.

1 . A semiconductor device, comprising:
 a semiconductor substrate of a first conductivity type;   a first well of the first conductivity type formed on a surface of said semiconductor substrate;   a second well of a second conductivity type formed on the surface of said semiconductor substrate;   a first transistor for a memory with a channel of the first conductivity type, formed in said first well;   a second transistor for the memory with a channel of the second conductivity type, formed in said second well; and   an embedded well of the second conductivity type formed directly under said first well.   
   
   
       2 . The semiconductor device according to  claim 1 , further comprising:
 a first transistor for a peripheral circuit with a channel of the first conductivity type, formed on the surface of said semiconductor substrate; and   a second transistor for the peripheral circuit with a channel of the first conductivity type, formed on the surface of said semiconductor substrate,   operating voltage of said first transistor for the memory and that of said first transistor for the peripheral circuit being equal to each other, and the operating voltage of said first transistor for the memory and said second transistor for the peripheral circuit are different from each other.   
   
   
       3 . A manufacturing method of a semiconductor device, comprising the step of forming a first transistor for a memory with a channel of a first conductivity type, a first transistor for a peripheral circuit with a channel of the first conductivity type and a second transistor for the peripheral circuit with a channel of the first conductivity type, on a surface of a semiconductor substrate,
 an impurity profile of the channel of the first transistor for the memory being made a total of that of the first transistor for the peripheral circuit and that of the second transistor for the peripheral circuit.   
   
   
       4 . The manufacturing method of the semiconductor device according to  claim 3 , wherein
 said step of forming the first transistor for the memory, the first transistor for the peripheral circuit and the second transistor for the peripheral circuit comprises the steps of:   introducing an impurity of the first conductivity type into a region of the first transistor for the memory and a region of the first transistor for the peripheral circuit; and   introducing an impurity of the first conductivity type into the region of the first transistor for the memory and a region of the second transistor for the peripheral circuit.   
   
   
       5 . The manufacturing method of the semiconductor device according to  claim 3 , wherein operating voltage of the first transistor for the memory is made equal to that of the first transistor for the peripheral circuit, and is made different from that of the second transistor for the peripheral circuit. 
   
   
       6 . The manufacturing method of the semiconductor device according to  claim 3 , wherein
 a conductivity type of the semiconductor substrate is made the first conductivity type, and   said step of forming the first transistor for the memory, the first transistor for the peripheral circuit and the second transistor for the peripheral circuit comprises the steps of:   forming an embedded well of the second conductivity type inside the semiconductor substrate;   forming a first well of the first conductivity type on the embedded well on the surface of the semiconductor substrate;   forming a second well of the second conductivity type at a position spaced from the first well on the surface of the semiconductor substrate; and   forming the first transistor for the memory in the first well and forming a second transistor for the memory with the channel of the second conductivity type in the second well.   
   
   
       7 . A manufacturing method of a semiconductor device, comprising the steps of:
 forming an embedded well of a second conductivity type inside a semiconductor substrate of a first conductivity type;   forming a first well of the first conductivity type on the embedded well on the surface of the semiconductor substrate;   forming a second well of the second conductivity type at a position spaced from the first well on the surface of the semiconductor substrate; and   forming a first transistor for a memory with a channel of the first conductivity type in the first well, and forming a second transistor for the memory with a channel of the second conductivity type in the second well.   
   
   
       8 . The manufacturing method of the semiconductor device according to  claim 7 , wherein
 said step of forming the first transistor for the memory and the second transistor for the memory comprises the step of forming first and second transistors for a peripheral circuits with channels of the first conductive type on the surface of the semiconductor substrate, and   operating voltage of the first transistor for the memory is made equal to that of the first transistor for the peripheral circuit, and is made different from that of the second transistor for the peripheral circuit.   
   
   
       9 . The manufacturing method of the semiconductor device according to  claim 3 , wherein a static random access memory is formed as the memory. 
   
   
       10 . The manufacturing method of the semiconductor device according to  claim 3 , wherein said step of forming the first transistor for the memory, the first transistor for the peripheral circuit and the second transistor for the peripheral circuit comprises the step of forming a non-volatile memory cell with a channel of the first conductivity type on the surface of the semiconductor substrate. 
   
   
       11 . The manufacturing method of the semiconductor device according to  claim 6 , wherein a structure of the first and the second wells is a triple-well structure. 
   
   
       12 . The manufacturing method of the semiconductor device according to  claim 3 , wherein the first conductivity type is p-type, and the second conductivity type is n-type.