Highly Conductive Shallow Junction Formation
Abstract
The invention relates to a method of forming a shallow junction. The method ( 100 ) comprises forming source/drain extension regions with a non-amorphizing tail implant ( 105 ) which is annealed conventionally (spike/RTP) and amorphizing implant which is re-grown epitaxially(SPER) ( 110 ). The non-amorphizing tail implant is generally annealed ( 106 ) before a doped amorphous layer for SPE is formed ( 107 ). SPE provides a high active dopant concentration in a shallow layer. The non-amorphizing tail implant ( 105 ) expands the source/drain extension region beyond the range dictated by the SPE-formed layer and keeps the depletion region of the P-N junction away from where end-of-range defects form during the SPE process. Thus, the SPE-formed layer primarily determines the conductivity of the junction while the tail implant determines the location of the depletion region. End-of-range defects form, but are not in a position to cause significant reverse bias leakage.
Claims
exact text as granted — not AI-modified1 - 16 . (canceled)
17 . A semiconductor device, comprising:
a gate having a gate electrode, a channel region below the gate electrode, a source region and a drain region to either side of the channel, and source and drain extension regions bridging small gaps between the source and drain regions and the channel region, the source and drain extension regions comprising a conductive layer having active dopant concentrations of at least about 2 . 0 × 10 20 atoms/cm 3 ; and end-of-range defects at the limit of the conductive layer; wherein the extension regions extend beyond the conductive layer and the end-of-range defects are displaced from depletion regions formed between the source/drain extension regions and the channel regions beneath the gates.
18 . The semiconductor device of claim 17 , wherein the conductive layer has active dopant concentrations of at least about 2 . 5 × 10 20 atoms/cm 3 .
19 . The method of claim 17 , wherein the channel is about 45 nm wide or less.
20 . The method of claim 17 , wherein the conductive layer in no more than about 200 Å deep.Join the waitlist — get patent alerts
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