Nonvolatile semiconductor storage device with charge storage layer and its manufacturing method

Abstract

A nonvolatile semiconductor storage device includes a semiconductor substrate, a charge storage layer formed above the semiconductor substrate, a control gate formed above the charge storage layer, a spacer layer formed above the control gate and a word gate formed above a side of the control gate and the spacer layer. Atop surface of the spacer layer is lower as the top surface of the spacer layer is farther from the word gate.

1 . A nonvolatile semiconductor storage device, comprising:
 a semiconductor substrate;   a charge storage layer formed above the semiconductor substrate;   a control gate formed above the charge storage layer;   a spacer layer formed above the control gate; and   a word gate formed above a side of the control gate and the spacer layer,   wherein a top surface of the spacer layer is lower as the top surface of the spacer layer is farther from the word gate.   
     
     
         2 . The nonvolatile semiconductor storage device according to  claim 1 , wherein a top surface of the control gate is substantially flat. 
     
     
         3 . The nonvolatile semiconductor storage device according to  claim 1 , wherein a height of a top surface of the word gate from the semiconductor substrate is higher than a height of a top surface of the control gate from the semiconductor substrate. 
     
     
         4 . The nonvolatile semiconductor storage device according to  claim 1 , wherein the charge storage layer includes:
 a first silicon oxide layer;   a silicon nitride layer formed above the first silicon oxide layer; and   a second silicon oxide layer formed above the silicon nitride layer.   
     
     
         5 . The nonvolatile semiconductor storage device according to  claim 1 , further comprising:
 a first diffusion layer formed on the semiconductor substrate; and   a second diffusion layer formed on the semiconductor substrate,   wherein the charge storage layer and the word gate are disposed between the first diffusion layer and the second diffusion layer.   
     
     
         6 . The nonvolatile semiconductor storage device according to  claim 5 , further comprising:
 a first silicide layer formed on the word gate;   a second silicide layer formed on the first diffusion layer; and   a third silicide layer formed on the second diffusion layer.   
     
     
         7 . The nonvolatile semiconductor storage device according to  claim 1 , further comprising a silicide layer formed on a top surface of the control gate. 
     
     
         8 . The nonvolatile semiconductor storage device according to  claim 6 , further comprising a fourth silicide layer formed on a top surface of the control gate. 
     
     
         9 . The nonvolatile semiconductor storage device according to  claim 1 , wherein the charge storage layer comprises a first charge storage layer,
 wherein the control gate comprises a first control gate,   wherein the spacer layer comprises a first spacer layer,
 wherein the nonvolatile semiconductor storage device further comprises: 
 a second charge storage layer formed above the semiconductor substrate, the first charge storage layer and the second charge storage layer being disposed symmetrically with respect to the word gate; 
 a second control gate formed above the second charge storage layer, the first control gate and the second control gate being disposed symmetrically with respect to the word gate; and 
 a second spacer layer formed above the second control gate, the first spacer layer and the second spacer layer being disposed symmetrically with respect to the word gate, 
   wherein a top surface of the second spacer layer is lower as the top surface of the second spacer layer is farther from the word gate.   
     
     
         10 . The nonvolatile semiconductor storage device according to  claim 9 , further comprising:
 a first silicide layer formed on a top surface of the first control gate; and   a second silicide layer formed on a top surface of the second control gate.   
     
     
         11 . The nonvolatile semiconductor storage device according to  claim 9 , further comprising:
 a first diffusion layer formed on the semiconductor substrate; and   a second diffusion layer formed on the semiconductor substrate,   wherein the first charge storage layer, the second charge storage layer and the word gate are disposed between the first diffusion layer and the second diffusion layer.   
     
     
         12 . A nonvolatile semiconductor storage device, comprising:
 a semiconductor substrate;   a charge storage layer formed above the semiconductor substrate;   a control gate formed above the charge storage layer;   a spacer layer formed above the control gate; and   a word gate formed above a side of the control gate and the spacer layer,   wherein a width of the spacer layer is narrower as the width of the spacer layer is farther from the control gate.   
     
     
         13 . The nonvolatile semiconductor storage device according to claim. 12 , wherein a top surface of the control gate is substantially flat. 
     
     
         14 . The nonvolatile semiconductor storage device according to  claim 12 , further comprising a silicide layer formed on a top surface of the control gate. 
     
     
         15 . The nonvolatile semiconductor storage device according to  claim 12 , wherein the charge storage layer comprises a first charge storage layer,
 wherein the control gate comprises a first control gate,   wherein the spacer layer comprises a first spacer layer,   wherein the nonvolatile semiconductor storage device further comprises:
 a second charge storage layer formed above the semiconductor substrate, the first charge storage layer and the second charge storage layer being disposed symmetrically with respect to the word gate; 
   a second control gate formed above the second charge storage layer, the first control gate and the second control gate being disposed symmetrically with respect to the word gate; and   a second spacer layer formed above the second control gate, the first spacer layer and the second spacer layer being disposed symmetrically with respect to the word gate,   wherein a width of the second spacer layer is narrower as the width of the second spacer layer is farther from the second control gate.   
     
     
         16 . The nonvolatile semiconductor storage device according to  claim 15 , further comprising:
 a first silicide layer formed on a top surface of the first control gate; and   a second silicide layer formed on a top surface of the second control gate.   
     
     
         17 . A nonvolatile semiconductor storage device, comprising:
 a semiconductor substrate;   a charge storage layer formed above the semiconductor substrate;   a control gate formed above the charge storage layer;   a spacer layer formed above the control gate; and   a word gate formed above a side of the control gate and the spacer layer,   wherein a height of the spacer layer from a top surface of the control gate is lower as the top surface of the spacer layer is farther from the word gate.   
     
     
         18 . The nonvolatile semiconductor storage device according to  claim 17 , wherein a top surface of the control gate is substantially flat. 
     
     
         19 . The nonvolatile semiconductor storage device according to  claim 17 , further comprising a silicide layer formed on a top surface of the control gate. 
     
     
         20 . The nonvolatile semiconductor storage device according to  claim 17 , wherein the charge storage layer comprises a first charge storage layer,
 wherein the control gate comprises a first control gate,   wherein the spacer layer comprises a first spacer layer,   wherein the nonvolatile semiconductor storage device further comprises:
 a second charge storage layer formed above the semiconductor substrate, the first charge storage layer and the second charge storage layer being disposed symmetrically with respect to the word gate; 
 a second control gate formed above the second charge storage layer, the first control gate and the second control gate being disposed symmetrically with respect to the word gate; and 
 a second spacer layer formed above the second control gate, the first spacer layer and the second spacer layer being disposed symmetrically with respect to the word gate, 
 wherein a height of the spacer layer from a top surface of the second control gate is lower as the top surface of the second spacer layer is farther from the word gate.