Range-Matching Cell and Content Addressable Memories Using the Same

Abstract

A range-matching cell (RMC) includes bit lines (BL); a word line (WL); a match line (ML); search lines (SL); a memory cell ( 100 ); a first comparator ( 110 ) connected to the memory cell; a second comparator ( 120 ) connected to the first comparator, a ground voltage and a predetermined voltage. The comparators conduct a comparing operation in responsive to operator data. Instead of the conventional TCAMs employing 0, 1, and X (don't care) bit, a CAM utilizing the RMC can conduct a comparing operation with less memory by storing the operator data 0 and 1 in advance. Accordingly, memory-use efficiency can be increased.

1 . A range-matching cell comprising:
 a pair of a bit line and a complementary bit line;   a word line;   a memory cell connected to the word line and the bit lines for storing data transmitted via the bit lines when the word line is activated;   a match line;   a pair of a search line and a complementary search line;   a first transistor connected in series to the match line;   a first comparator connected to the memory cell, the match line and the search lines for controlling on or off the first transistor in response to the stored data in the memory cell and searched data transmitted via the search lines; and   a second comparator for connecting the match line to a ground voltage or a predetermined voltage based on the searched data and a stored operator data when the first transistor is turned off, wherein the operator data including logic values of 0 and 1.   
   
   
       2 . The range-matching cell of  claim 1 , wherein the memory cell includes:
 storing means for storing the data; and   connecting means for coupling the bit lines to the storing means in order to provide the stored data received by the bit lines to the storing means.   
   
   
       3 . The range-matching cell of  claim 2 , wherein the storing means includes a cross-coupled inverter. 
   
   
       4 . The range-matching cell of  claim 2 , wherein connecting means includes a first and a second pass gate, wherein the pass gates are connected to the word line. 
   
   
       5 . The range-matching cell of  claim 1 , wherein the first comparator turns on the first transistor if the stored data matches the searched data, and, if not, turns off the first transistor. 
   
   
       6 . The range-matching cell of  claim 1 , wherein the second comparator connects the match line to the ground voltage if the searched data matches the operator data, and, if not, the second comparator connects the match line to the predetermined voltage. 
   
   
       7 . The range-matching cell of  claim 2 , wherein the first comparator is provided with a second transistor for connecting the search line to the first transistor, and the second transistor has a gate connected to the storing means. 
   
   
       8 . The range-matching cell of  claim 1 ,
 wherein the second comparator is provided with a third, a fourth and a fifth transistor for connecting the match line in series to the ground voltage,   wherein the third transistor connects the match line to the fourth transistor and has a gate connected to the first comparator;   wherein the fourth transistor connects the third transistor to the fifth transistor and has a gate connected to the search line; and   wherein the fifth transistor connects the fourth transistor to the ground voltage and has a gate for receiving the operator data.   
   
   
       9 . The range-matching cell of  claim 1 , wherein the second comparator includes:
 a sixth and a seven transistor for connecting the predetermined voltage in series to the match line;   an eighth transistor;   a third pass gate; and   a forth pass gate,   wherein the sixth transistor has a gate connected to the first comparator,   wherein the seventh transistor has a gate for accepting an OR-operated result of the first and the second operator data;   wherein the eighth transistor is connected to the match line, the third and the forth pass gates, and has a gate for accepting an inverted output of the first comparator;   wherein the third pass gate is connected to the complementary search line and the eighth transistor, and has a gate for receiving the first operator data; and   wherein the forth pass gate is connected to the search line and the eighth transistor, and has a gate for receiving the second operator data.   
   
   
       10 . A Content Addressable Memory (CAM) comprising:
 a match line;   a word line;   N pairs of bit lines and complementary bit lines arranged in the column direction;   N pairs of search lines and complementary search lines;   N range-matching cells connected to the match line, the word line and each of the N pairs of the bit lines,   wherein each range-matching cell includes:   a memory cell, connected to the word line and the bit lines, for storing data transmitted via the bit lines when the word line is activated;   a first transistor connected in series to the match line;   a first comparator connected to the memory cell, the match line and the search lines for controlling turning on or off the first transistor in response to the stored data in the memory cell and searched data transmitted via the search lines; and   a second comparator for connecting the match line to a ground voltage or a predetermined voltage based on the searched data and a stored operator data when the first transistor is turned off, wherein the operator data including logic values of 0 and 1.   
   
   
       11 . The CAM of  claim 10 , wherein one end of the match line is connected to a ground voltage and the other end of the match line is connected to the match line. 
   
   
       12 . The CAM of  claim 10 , wherein the memory cell includes:
 storing means for storing the data; and   connecting means for coupling the bit lines to the storing means in order to provide the stored data received by the bit lines to the storing means.   
   
   
       13 . The CAM of  claim 12 , wherein the storing means includes a cross-coupled inverter. 
   
   
       14 . The CAM of  claim 12 , wherein connecting means includes a first and a second pass gate, and the first and the second pass gates are connected to the word line. 
   
   
       15 . The CAM of  claim 10 , wherein the first comparator turns on the first transistor if the stored data matches the searched data, and, if not, turns off the first transistor. 
   
   
       16 . The CAM of  claim 10 , wherein the second comparator connects the match line to the ground voltage if the searched data matches the operator data, and, if not, the second comparator connects the match line to the predetermined voltage. 
   
   
       17 . The CAM of  claim 12 , wherein the first comparator is provided with a second transistor for connecting the search line to the first transistor, the second transistor having a gate connected to the storing means. 
   
   
       18 . The CAM of  claim 10 , wherein the second comparator includes a third, a fourth and a fifth transistor for connecting the match line in series to the ground voltage, wherein the third transistor connects the match line to the fourth transistor, and has a gate connected to the first comparator;
 wherein the fourth transistor connects the third transistor to the fifth transistor, and has a gate connected to the search line; and   wherein the fifth transistor connects the fourth transistor to the ground voltage, and has a gate for receiving the operator data.   
   
   
       19 . The CAM of  claim 10 , wherein the second comparator includes:
 a sixth and a seventh transistor for connecting the predetermined voltage in series to the match line;   an eighth transistor;   a third pass gate; and   a forth pass gate,   wherein the sixth transistor has a gate connected to the first comparator,   wherein the seventh transistor has a gate for accepting an OR-operated result of the first and the second operator data;   wherein the eighth transistor is connected to the match line, the third and the forth pass gates, and has a gate for accepting an inverted output of the first comparator;   wherein the third pass gate is connected to the complementary search line and the eighth transistor, and has a gate for receiving the first operator data; and   wherein the forth pass gate is connected to the search line and the eighth transistor, and has a gate for receiving the second operator data.