Abnormal Condition Detection Circuit, Integrated Circuit Card Having the Circuit, and Method of Operating CPU

Abstract

An abnormal condition detection circuit, an integrated circuit (IC) card having a central processing unit (CPU), and a method of operating the CPU, allow the CPU to be reset when an abnormal condition is detected in the IC card. The IC card includes the CPU, a non-volatile memory, an abnormal condition detection circuit, and a reset signal generator. The IC card includes detectors that detect a corresponding abnormal condition in the IC card, and an enable signal generation circuit that generates a reset enable signal and an interrupt enable signal in response to an interrupt control signal and a detection signal output from at least one of the detectors. The reset signal generator generates a reset signal in response to the reset enable signal. The CPU is reset in response to the reset signal and interrupted in response to the interrupt enable signal.

1 . An integrated circuit card comprising:
 an integrated circuit card substrate, the integrated circuit card substrate comprising:   a central processing unit;   a plurality of detectors, a respective one of which is configured to detect a corresponding abnormal condition in the integrated circuit card and to output a detection signal indicative of the abnormal condition;   an enable signal generation circuit that is configured to generate a reset enable signal and an interrupt enable signal, in response to an interrupt control signal and the detection signal output from at least one of the detectors; and   a reset signal generator that is configured to generate a reset signal in response to the reset enable signal,   wherein the central processing unit is configured to be reset in response to the reset signal and to be interrupted in response to the interrupt enable signal.   
   
   
       2 . A method of operating a central processing unit of an integrated circuit card, comprising:
 detecting at least one abnormal condition in the integrated circuit card and generating at least one detection signal indicative of the at least one abnormal condition;   generating a reset enable signal and an interrupt enable signal in response to a reset control signal and the at least one detection signal;   generating a reset signal in response to the reset enable signal;   resetting the central processing unit in response to the reset signal; and   interrupting the central processing unit in response to the interrupt enable signal.