Dynamic Bus Parking

Abstract

Systems and methods of power management provide for issuing a power saving message from a processor toward a controller and using the controller to conduct a power saving activity in response to the power saving message. In one embodiment, the power saving message is issued by de-asserting a bus arbitration signal and the power saving activity can include disabling one or more input buffers of the controller.

1 . An apparatus comprising:
 a controller; and   a processor having bus logic to issue a power saving message, the controller having power management logic to conduct a power saving activity in response to the power saving message.   
   
   
       2 . The apparatus of  claim 1 , wherein the bus logic is to determine whether to issue the power saving message based on an operating frequency of the processor. 
   
   
       3 . The apparatus of  claim 2 , wherein the bus logic is to determine whether to issue the power saving message based on a ratio of the operating frequency of the processor to an operating frequency of a bus disposed between the processor and the controller. 
   
   
       4 . The apparatus of  claim 2 , further including a plurality of processors, the operating frequency to be shared by each of the plurality of processors. 
   
   
       5 . The apparatus of  claim 1 , wherein the bus logic is to determine whether to issue the power saving message based on an idleness of a bus disposed between the processor and the controller. 
   
   
       6 . The apparatus of  claim 5 , wherein the bus logic is to count a number of idle clock cycles on the bus and compare the number of idle clock cycles to a counter value. 
   
   
       7 . The apparatus of  claim 6 , wherein the bus logic is to retrieve the counter value from a programmable memory location. 
   
   
       8 . The apparatus of  claim 1 , wherein the power saving message is to include a de-assertion of a bus arbitration signal. 
   
   
       9 . The apparatus of  claim 1 , wherein the power saving activity is to be selected from a group comprising disabling an internal component of the controller and disabling an external component that is managed by the controller. 
   
   
       10 . The apparatus of  claim 9 , wherein the internal component of the controller is to be selected from a group comprising an input buffer and a functional block. 
   
   
       11 . The apparatus of  claim 9 , wherein the external component is to include a memory device. 
   
   
       12 . The apparatus of  claim 1 , further including a chipset memory controller hub, the memory controller hub including the controller. 
   
   
       13 . A method comprising:
 issuing a power saving message from a processor toward a controller; and   using the controller to conduct a power saving activity in response to the power saving message.   
   
   
       14 . The method of  claim 13 , further including determining whether to issue the power saving message based on an operating frequency of the processor. 
   
   
       15 . The method of  claim 14 , further including determining whether to issue the power saving message based on a ratio of the operating frequency of the processor to an operating frequency of a bus disposed between the processor and the controller. 
   
   
       16 . The method of  claim 14 , wherein the operating frequency is shared by each of a plurality of processors. 
   
   
       17 . The method of  claim 13 , further including determining whether to issue the power saving message based on an idleness of a bus disposed between the processor and the controller. 
   
   
       18 . The method of  claim 17 , further including: counting a number of idle clock cycles on the bus; and comparing the number of idle clock cycles to a counter value. 
   
   
       19 . The method of  claim 18 , further including retrieving the counter value from a programmable memory location. 
   
   
       20 . The method of  claim 13 , wherein the issuing includes de-asserting a bus arbitration signal. 
   
   
       21 . The method of  claim 13 , wherein the using is selected from a group comprising disabling an internal component of the controller and disabling an external component that is managed by the controller. 
   
   
       22 . A system comprising:
 a small outline dual inline memory module (SODIMM);   a chipset coupled to the SODIMM; and   a processor coupled to the chipset, the processor having bus logic to issue a power saving message, the chipset having power management logic to conduct a power saving activity in response to the power saving message.   
   
   
       23 . The system of  claim 22 , wherein the bus logic is to determine whether to issue the power saving message based on an operating frequency of the processor. 
   
   
       24 . The system of  claim 23 , wherein the bus logic is to determine whether to issue the power saving message based on a ratio of the operating frequency of the processor to an operating frequency of a bus disposed between the processor and the chipset. 
   
   
       25 - 30 . (canceled)