Data processor memory circuit

Abstract

A memory circuit for use in a data processing circuit is described, in which memory cells have at least two states, each state being determined by both a first voltage level corresponding to a first supply line and a second voltage level corresponding to a second supply line. The memory circuit comprises a readable state in which information stored in a memory cell is readable and an unreadable state in which information stored in said memory cell is reliably retained but unreadable. Changing the first voltage level but keeping the second voltage level substantially constant effects a transition between the readable state and the unreadable state. In use, the static power consumption of the memory cell in the unreadable state is less than static power consumption of the memory cell in the readable state.

1 . A memory circuit comprising:
 at least one memory cell having:   (i) an active state in which information stored in said at least one memory cell is active; and   (ii) a retention state in which information stored in at least one memory cell is retained but retention, wherein static power consumption of said at least one memory cell in said retention state is less than static power consumption of said at least one memory cell in said active state, said memory circuit comprising at least one memory cell array, each memory cell array having a plurality of said memory cells that are collectively settable to said active state or said retention state; and   a mode controller operable to set said at least one memory cell array to said retention state.   
   
   
       2 . A memory circuit as claimed in  claim 1 , wherein at least one of a first voltage level and a second voltage level determine whether said at least one memory cell is in said active state or in said retention state said first voltage level corresponds to a first supply line and said second voltage level corresponds to a second supply line. 
   
   
       3 . A memory circuit as claimed in  claim 1 , in which said memory circuit has an off-state in which stored information is lost. 
   
   
       4 . A memory circuit according to  claim 1 , wherein said memory circuit is a cache memory circuit and wherein said at least one memory cell array is a respective cache line. 
   
   
       5 . A memory circuit according to  claim 1 , wherein said memory circuit is a cache memory circuit having a plurality of cache sub-banks and wherein said at least one memory cell array is a respective cache sub-bank. 
   
   
       6 . A memory circuit according to  claim 5 , comprising a pre-charge circuit responsive to a pre-charge signal and comprising a logic gate operable to gate said pre-charge signal with a signal for changing a cache sub-bank from said retention state to said active state. 
   
   
       7 . A memory circuit according to  claim 5 , comprising a sub-bank prediction buffer operable to predict which of said plurality of cache sub-banks will next be accessed after a currently active cache sub-bank and hence should next be set to said active state. 
   
   
       8 . A memory circuit according to  claim 7 , wherein each entry of said sub-bank prediction buffer comprises an instruction address of an instruction immediately prior to an instruction that leads to a change in a currently active cache sub-bank. 
   
   
       9 . A memory circuit as claimed in  claim 4 , wherein each cache line has an address tag that identifies data currently stored in that cache line and said address tag is extended to include at least one sub-bank predictor array element. 
   
   
       10 . A memory circuit as claimed in  claim 4 , wherein each cache line has an address tag that identifies data currently stored in a respective cache line, said address tag being settable to said active state or to said retention state in correspondence with a setting of the associated cache line in either said active state or said retention state. 
   
   
       11 . A memory circuit according to  claim 4 , comprising a voltage controller for a respective one of said cache lines. 
   
   
       12 . A memory circuit according to  claim 5 , comprising a voltage controller for a respective one of said cache sub-banks. 
   
   
       13 . A memory circuit as claimed in  claim 11 , wherein said voltage controller is operable to determine said second voltage of said at least one memory array in dependence upon a value of a active-status bit associated with a respective memory array. 
   
   
       14 . A memory circuit as claimed in  claim 1 , wherein said mode controller is operable to periodically reset all of said memory arrays to said retention state according to a predetermined reset time. 
   
   
       15 . A memory circuit as claimed in  claim 14 , wherein said predetermined reset time is adaptive such that it is dependent upon a performance impact threshold. 
   
   
       16 . A memory circuit as claimed in  claim 14 , wherein said mode controller is operable to set to retention mode only those cache lines that have not been accessed in a predetermined time window. 
   
   
       17 . A memory circuit as claimed in  claim 14 , in which said mode controller is operable to calculate a performance penalty for setting each memory array to said retention state and is further operable to calculate said reset time in dependence upon said performance penalty. 
   
   
       18 . A memory circuit as claimed in  claim 3 , wherein each memory cell comprises a plurality of complementary metal oxide semiconductor (CMOS) cell-transistors. 
   
   
       19 . A memory circuit as claimed in  claim 18 , wherein said changing of said first voltage level to effect said transition is facilitated by connecting at least one of said memory cell arrays both to a normal voltage supply by a first CMOS transistor and to a low voltage supply by a second CMOS transistor, said first CMOS transistor and said second CMOS transistor each having a threshold voltage that is substantially higher than a threshold voltage associated with said cell transistors and said retention state corresponds to the connection to said low voltage supply being effective whereas said active state corresponds to the connection to said normal voltage supply being effective. 
   
   
       20 . A memory circuit as claimed in  claim 18 , wherein each of said at least one memory cell arrays is connected to a read/write line via a CMOS pass-transistor having a threshold voltage that is substantially higher than a threshold voltage associated with said cell transistors. 
   
   
       21 . A memory circuit as claimed in  claim 20 , wherein at least one of a first voltage level and a second voltage level determine whether said at least one memory cell is in said active state or in said retention state said first voltage level corresponds to a first supply line and said second voltage level corresponds to a second supply line, and in which a capacitance of said first supply line is substantially less than a capacitance of said pass-transistor. 
   
   
       22 . A memory circuit as claimed in  claim 18 , wherein at least one of a first voltage level and a second voltage level determine whether said at least one memory cell is in said active state or in said retention state said first voltage level corresponds to a first supply line and said second voltage level corresponds to a second supply line, and wherein in said retention state, said first voltage level is settable to be substantially 1.5 times the value of the threshold voltage associated with said cell transistors. 
   
   
       23 . A memory circuit as claimed in  claim 1 , wherein said at least one memory array comprises circuitry operable to prevent any accesses to a respective memory array when said memory array is in said retention state. 
   
   
       24 . A memory circuit as claimed in  claim 1 , wherein said memory circuit is a static random access memory (SRAM) circuit and each of said at least one memory cell arrays comprises memory cells associated with a respective predetermined memory address range in SRAM. 
   
   
       25 . A memory circuit as claimed in  claim 1 , wherein said memory circuit is a tightly coupled memory (TCM) circuit. 
   
   
       26 . A memory circuit as claimed in  claim 2 , wherein a transition between said active state to said retention state is effected by changing said first voltage level such that it is lower in said retention state than in said active state. 
   
   
       27 . A memory circuit according to  claim 2 , wherein said second voltage level is set is ground level. 
   
   
       28 . A memory circuit comprising:
 at least one memory cell having:   (i) a being read state;   (ii) an active state in which information stored in said at least one memory cell is ready to be read in said being read state; and   (iii) a retention state in which information stored in at least one memory cell is retained but is not ready to be read in said being read state; wherein static power consumption of said at least one memory cell in said retention state is less than static power consumption of said at least one memory cell in said active state.   
   
   
       29 . A memory circuit as claimed in  claim 28 , wherein at least one of a first voltage level and a second voltage level determine whether said at least one memory cell is in said active state or in said retention state said first voltage level corresponds to a first supply line and said second voltage level corresponds to a second supply line. 
   
   
       30 . A memory circuit as claimed in  claim 28 , in which said memory circuit has an off-state in which stored information is lost. 
   
   
       31 . A memory circuit comprising:
 at least one memory cell having:   (i) an active state in which information stored in said at least one memory cell is ready to be read in a separate being read state; and   (ii) a retention state in which information stored in at least one memory cell is retained but is not ready to be read in a separate being read state;   wherein static power consumption of said at least one memory cell in said retention state is less than static power consumption of said at least one memory cell in said active state, said memory cell comprising at least one memory cell array, each memory cell array having a plurality of said memory cells that are collectively settable to said active state or said retention state.   
   
   
       32 . A memory circuit according to  claim 31 , wherein said memory circuit is a cache memory circuit and wherein said at least one memory cell array is a respective cache line. 
   
   
       33 . A memory circuit according to  claim 31 , wherein said memory circuit is a cache memory circuit having a plurality of cache sub-banks and wherein said at least one memory cell array is a respective cache sub-bank. 
   
   
       34 . A memory circuit according to  claim 33 , comprising a pre-charge circuit responsive to a pre-charge signal and comprising a logic gate operable to gate said pre-charge signal with a signal for changing a cache sub-bank from said retention state to said active state. 
   
   
       35 . A memory circuit according to  claim 33 , comprising a sub-bank prediction buffer operable to predict which of said plurality of cache sub-banks will next be accessed after a currently active cache sub-bank and hence should next be set to said active state. 
   
   
       36 . A memory circuit according to  claim 35 , wherein each entry of said sub-bank prediction buffer comprises an instruction address of an instruction immediately prior to an instruction that leads to a change in a currently active cache sub-bank. 
   
   
       37 . A memory circuit as claimed in  claim 32 , wherein each cache line has an address tag that identifies data currently stored in that cache line and said address tag is extended to include at least one sub-bank predictor array element. 
   
   
       38 . A memory circuit as claimed in  claim 32 , wherein each cache line has an address tag that identifies data currently stored in a respective cache line, said address tag being settable to said active state or to said retention state in correspondence with a setting of the associated cache line in either said active state or said retention state. 
   
   
       39 . A memory circuit according to  claim 32 , comprising a voltage controller for a respective one of said cache lines. 
   
   
       40 . A memory circuit according to  claim 33 , comprising a voltage controller for a respective one of said cache sub-banks. 
   
   
       41 . A memory circuit as claimed in  claim 39 , wherein said voltage controller is operable to determine said second voltage of said at least one memory array in dependence upon a value of a active-status bit associated with a respective memory array. 
   
   
       42 . A memory circuit as claimed in  claim 31 , comprising a mode controller operable to selectively set predetermined ones of a plurality of said memory cell arrays to said retention state. 
   
   
       43 . A memory circuit as claimed in  claim 42 , wherein said mode controller is operable to periodically reset all of said memory arrays to said retention state according to a predetermined reset time. 
   
   
       44 . A memory circuit as claimed in  claim 43 , wherein said predetermined reset time is adaptive such that it is dependent upon a performance impact threshold. 
   
   
       45 . A memory circuit as claimed in  claim 43 , wherein said mode controller is operable to set to retention mode only those cache lines that have not been accessed in a predetermined time window. 
   
   
       46 . A memory circuit as claimed in  claim 43 , in which said mode controller is operable to calculate a performance penalty for setting each memory array to said retention state and is further operable to calculate said reset time in dependence upon said performance penalty. 
   
   
       47 . A memory circuit as claimed in  claim 30 , wherein each memory cell comprises a plurality of complementary metal oxide semiconductor (CMOS) cell-transistors. 
   
   
       48 . A memory circuit as claimed in  claim 47 , wherein said changing of said first voltage level to effect said transition is facilitated by connecting at least one of said memory cell arrays both to a normal voltage supply by a first CMOS transistor and to a low voltage supply by a second CMOS transistor, said first CMOS transistor and said second CMOS transistor each having a threshold voltage that is substantially higher than a threshold voltage associated with said cell transistors and said retention state corresponds to the connection to said low voltage supply being effective whereas said active state corresponds to the connection to said normal voltage supply being effective. 
   
   
       49 . A memory circuit as claimed in  claim 47 , wherein each of said at least one memory cell arrays is connected to a read/write line via a CMOS pass-transistor having a threshold voltage that is substantially higher than a threshold voltage associated with said cell transistors. 
   
   
       50 . A memory circuit as claimed in  claim 49 , wherein at least one of a first voltage level and a second voltage level determine whether said at least one memory cell is in said active state or in said retention state said first voltage level corresponds to a first supply line and said second voltage level corresponds to a second supply line, and in which a capacitance of said first supply line is substantially less than a capacitance of said pass-transistor. 
   
   
       51 . A memory circuit as claimed in  claim 47 , wherein at least one of a first voltage level and a second voltage level determine whether said at least one memory cell is in said active state or in said retention state said first voltage level corresponds to a first supply line and said second voltage level corresponds to a second supply line, and wherein in said retention state, said first voltage level is settable to be substantially 1.5 times the value of the threshold voltage associated with said cell transistors. 
   
   
       52 . A memory circuit as claimed in  claim 31 , wherein said at least one memory array comprises circuitry operable to prevent any accesses to a respective memory array when said memory array is in said retention state. 
   
   
       53 . A memory circuit as claimed in  claim 31 , wherein said memory circuit is a static random access memory (SRAM) circuit and each of said at least one memory cell arrays comprises memory cells associated with a respective predetermined memory address range in SRAM. 
   
   
       54 . A memory circuit as claimed in  claim 31 , wherein said memory circuit is a tightly coupled memory (TCM) circuit. 
   
   
       55 . A memory circuit as claimed in  claim 29 , wherein a transition between said active state to said retention state is effected by changing said first voltage level such that it is lower in said retention state than in said active state. 
   
   
       56 . A memory circuit according to  claim 29 , wherein said second voltage level is set is ground level.