Semiconductor device arrangement and method

Abstract

A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor.

1 . A semiconductor device comprising:
 at least one power transistor; and   at least one gate resistor located between a gate of the power transistor and a connecting point in a drive circuit of the power transistor,   wherein a switchable element is additionally provided between the connecting point and a source of the power transistor.   
   
   
       2 . The semiconductor device of  claim 1 , wherein the switchable element maintains the connection between the connecting point and the source of the power transistor during a turn-off phase of the power transistor. 
   
   
       3 . The semiconductor device of  claim 1 , wherein the switchable element maintains the connection between the connecting point and the source of the power transistor during a turn-off phase and during an off state. 
   
   
       4 . The semiconductor device of  claim 1 , wherein the switchable element is a depletion MOSFET with its own gate connection, which is monolithically integrated into a body zone of the power transistor, wherein the gate connection of the MOSFET is electrically connected to the source of the power transistor. 
   
   
       5 . The semiconductor device of  claim 4 , wherein the drive point forms a source of the n-type depletion MOSFET and the source of the power transistor forms a drain of the n-type depletion MOSFET and the gate contact of the n-type depletion MOSFET is electrically connected to the source of the power transistor. 
   
   
       6 . The semiconductor device of  claim 1 , wherein the switchable element is a junction field effect transistor monolithically integrated into a body zone of the power transistor, its channel zone being represented by a shallow n-implantation, and wherein the channel zone can be depleted from the p-type region of the body zone. 
   
   
       7 . The semiconductor device of  claim 1 , wherein the switchable element is a junction field effect transistor structure integrated into the gate structure of the power transistor. 
   
   
       8 . The semiconductor device of  claim 1 , wherein the switchable element is a switching transistor driven by an AND gate with an inverted input, and wherein the output of the AND gate is electrically connected to the gate of the switching transistor. 
   
   
       9 . A semiconductor device arrangement comprising:
 a power transistor having a gate;   a connecting point in a drive circuit of the power transistor;   a gate resistor of the power transistor located between the connecting point and the gate; and   wherein a switchable element is located between the connecting point and a source of the power transistor and is connected to the gate such that the parasitic inductances between the connecting point and the source are bridged in the turn-off phase of the power transistor at steep switching edges.   
   
   
       10 . The semiconductor device arrangement of  claim 9 , wherein the switchable element includes two transistors, having body zones that are arranged such that they block anti-serially. 
   
   
       11 . The semiconductor device arrangement of  claim 10 , wherein the two transistors have a common gate electrically connected to the gate of the power transistor. 
   
   
       12 . The semiconductor device arrangement of  claim 10 , wherein the two transistors have drains that form a switching node. 
   
   
       13 . The semiconductor device arrangement according to of  claim 9 , wherein the switchable element is installed as a monolithically integrated component into a lateral field effect power transistor. 
   
   
       14 . A semiconductor device arrangement comprising:
 a connecting point of a power transistor;   a gate of the power transistor;   a gate resistor of the power transistor located between the connecting point and the gate; and   a drive circuit, wherein a switchable element in the drive circuit is monolithically integrated into the power transistor and comprises a gate which is externally accessible and which can be controlled by a complementary driver pulse such that the parasitic inductances between the connecting point and a source of the power transistor are bridged by means of the switchable element at a steep switching edge.   
   
   
       15 . The semiconductor device arrangement of  claim 14 , wherein the switchable element comprises a source and a drain and the drain is electrically connected to the connecting point while the source is connected to the source of the power transistor. 
   
   
       16 . The semiconductor device arrangement of  claim 14 , wherein a p-type well of the switchable element is provided in an n-type semiconductor material of the power transistor. 
   
   
       17 . A semiconductor device arrangement comprising:
 a connecting point of a power transistor;   a gate of the power transistor;   a gate resistor of the power transistor located between the connecting point and the gate; and   a drive circuit, wherein a switchable element in the drive circuit includes an operational amplifier, having first and second inputs electrically connected to the connecting point and to the gate of the power transistor respectively, and the output of which is electrically connected to the gate of the switchable element, so that parasitic inductances between the connecting point and a source of the power transistor are bridged by means of the switchable element at a steep switching edge.   
   
   
       18 . A method for the production of a semiconductor device arrangement with a switchable element in the drive circuit, comprising:
 providing a power transistor with parasitic inductances between a connecting point and a source and with a gate resistor between the connecting point and the gate;   producing a switchable element which, at a steep switching edge, bridges the inductances between the connecting point and the source in a turn-off phase of the power transistor.   
   
   
       19 . The method of  claim 18 , wherein a first and a second n-channel MOSFET are first produced in a semiconductor body with a common gate and a common drain, their first and second body diodes being connected back to back. 
   
   
       20 . The method according to of  claim 19 , further comprising:
 connecting the common gate to the gate of the power transistor;   connecting the first source of the first MOSFET to the connecting point; and   connecting the second source of the second MOSFET to the gate of the power transistor.   
   
   
       21 . The method according to of  claim 18 , further comprising:
 providing a lateral FET as a power transistor; and   monolithically integrating the first and second n-channel MOSFETs into the semiconductor body of the FET.