Semiconductor Circuit Device

Abstract

A semiconductor circuit device is provided which can attain more stable operations against noise in a data communication system without increasing the power consumption of an overall system, thereby improving the reliability of data communication. For a demodulation baseband signal (S 11 ) obtained by performing digital processing on an output signal (S 6 ) from an AD converter ( 6 ), the maximum value (S 12 ) and the minimum value (S 13 ) are detected as digital values by a maximum value holding circuit ( 11 ) and a minimum value holding circuit ( 12 ), an averaging circuit ( 13 ) obtains an average value (intermediate value) of the maximum value and the minimum value and detects a frequency offset amount (S 14 ), and the frequency offset amount is fed back to a threshold value of data decision ( 14 ), so that binarized demodulation data (S 15 ) is outputted in which the offset of the demodulation baseband signal is corrected.

1 - 11 . (canceled) 
   
   
       12 . A semiconductor circuit for demodulating a high-frequency signal into digital data, comprising:
 an AD converter converting an analog signal into a digital signal,   a digital IQ demodulator performing quadrature demodulation on the digital signal,   an F-V converter circuit converting a frequency of an output signal from the digital IQ demodulator into a voltage and outputting a converted signal as a demodulation baseband signal,   a frequency offset detector outputting a frequency offset amount given by averaging a maximum value of the demodulation baseband signal and a minimum value of the demodulation baseband signal, and   an offset corrector correcting a frequency offset on the demodulation baseband signal by using the frequency offset amount.   
   
   
       13 . The semiconductor circuit according to  claim 12 , further comprising:
 a mixer converting a frequency of the high-frequency signal into an intermediate frequency between the frequency of the high-frequency signal and a frequency of a reference frequency signal, and   a PLL generating the reference frequency signal.   
   
   
       14 . The semiconductor circuit according to  claim 13 , further comprising a PLL frequency corrector correcting a frequency of the frequency reference signal by using the frequency offset amount. 
   
   
       15 . The semiconductor circuit according to  claim 12 , further comprising a feedback gain circuit using the frequency offset amount as a feedback signal to a threshold value for deciding data of the demodulation baseband signal. 
   
   
       16 . The semiconductor circuit according to  claim 12 , further comprising a feedback gain circuit providing a feedback signal, which is the frequency offset amount multiplied by a gain, to a threshold value for deciding data of the demodulation baseband signal. 
   
   
       17 . The semiconductor circuit according to  claim 12 , further comprising an operation controller circuit periodically operating the frequency offset detector, and a timer counter counting a duty cycle of the frequency offset detector. 
   
   
       18 . The semiconductor circuit according to  claim 17 , further comprising a counting period storage device storing a value for setting a counting period of the timer counter at the value. 
   
   
       19 . The semiconductor circuit according to  claim 18 , further comprising a frequency offset amount storage device storing the frequency offset amount as a frequency offset value, wherein the operation controller circuit updates the frequency offset value. 
   
   
       20 . The semiconductor circuit according to  claim 19 , further comprising a comparator outputting a comparative value between the frequency offset value in the frequency offset amount storage device and the frequency offset amount currently outputted by the frequency offset detector. 
   
   
       21 . The semiconductor circuit according to  claim 20 , wherein the counting period storage device stores a count set value according to the comparative value, and
 the operation controller circuit changes the duty cycle of the frequency offset detector.   
   
   
       22 . The semiconductor circuit according to  claim 21 , wherein the operation controller circuit generates a control signal according to the comparative value for controlling update of the frequency offset value. 
   
   
       23 . The semiconductor circuit according to  claim 17 , further comprising an F detector circuit deciding a period of the timer counter, and a bit mask circuit masking specific bits of the demodulation baseband signal according to the period decided by the F detector circuit.