US2009203211A1PendingUtilityA1

Multi-chamber system having compact installation set-up for an etching facility for semiconductor device manufacturing

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Apr 21, 1998Filed: Apr 17, 2009Published: Aug 13, 2009
Est. expiryApr 21, 2018(expired)· nominal 20-yr term from priority
H10P 72/0461H10P 72/0458H10P 72/0456H10P 72/0454H10P 72/0452H10P 50/00Y10S414/141Y10S414/137Y10S414/139Y10S414/135
58
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A multi-chamber system of an etching facility for manufacturing semiconductor devices occupies a minimum amount of floor space in a clean room by installing a plurality of processing chambers in multi-layers and in parallel along a transfer path situated between the processing chambers. The multi-layers number 2 to 5 , and the transfer path can be rectangular in shape and need only be slightly wider than the diameter of a wafer. The total width of the multi-chamber system is the sum of the width of one processing chamber plus the width of the transfer path.

Claims

exact text as granted — not AI-modified
1 - 4 . (canceled) 
   
   
       5 . A method of manufacturing semiconductor devices in a multi-chamber wafer processing system, comprising:
 providing a first wafer on a cassette stage;   maintaining a rectangular wafer transfer path that is adjacent to and separate from the cassette stage without a vacuum, the transfer path providing space for transportation of the first wafer;   transferring the first wafer through the transfer path using a transfer mechanism located in the rectangular wafer transfer path from the cassette stage to a load lock chamber that is adjacent to the wafer transfer path, the load lock chamber aligned in parallel with a long side of the transfer path;   providing a low vacuum pressure in the load lock chamber;   transferring the first wafer from the load lock chamber directly to one of a plurality of processing chambers adjacent to the load lock chamber using a transfer arm installed in the load lock chamber;   etching the first wafer in the one of a plurality of processing chambers;   transferring the first wafer from the one of a plurality of processing chambers to the load lock chamber using the transfer arm; and   transferring the first wafer in the direction opposite to the one of the processing chambers through the wafer transfer path without a vacuum using the transfer mechanism,   wherein the load lock chamber is configured to receive a plurality of wafers from the transfer mechanism.   
   
   
       6 . The method of  claim 5 , further comprising verifying a high vacuum pressure in the one of the plurality of processing chambers before etching the first wafer. 
   
   
       7 . The method of  claim 5 , wherein the processing chambers are aligned in parallel with the long side of the wafer transfer path. 
   
   
       8 . The method of  claim 5 , further comprising transferring a second wafer from the cassette stage to an area next to the first wafer by the transfer mechanism through the rectangular wafer transfer path, the rectangular wafer transfer path providing a space for transportation of the second wafer without a vacuum between the cassette stage and the load lock chamber, the first and second wafers being aligned to the rectangular wafer transfer path in parallel.

Join the waitlist — get patent alerts

Track US2009203211A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.