Vertical system integration

Abstract

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

1 . A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:
 a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of integrated circuits of at least one integrated circuit type;   wherein the second stacked integrated circuit comprises at least one integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more integrated circuit of said integrated circuit type than said second stacked integrated circuit, the integrated circuits of said integrated circuit type within the first stacked integrated circuit being of substantially the same design as the integrated circuits of said integrated circuit type within the second stacked integrated circuit.   
   
   
       2 . The apparatus of  claim 1 , wherein the integrated circuits of said integrated circuit type within the first stacked integrated circuit being of identical design as the integrated circuits of said integrated circuit type within the second stacked integrated circuit. 
   
   
       3 . The apparatus of  claim 1 , wherein at least one of the integrated circuits of the first stacked integrated circuit comprises reconfiguration circuitry. 
   
   
       4 . The apparatus of  claim 1 , wherein at least one of the plurality of integrated circuits of the first stacked integrated circuit provides at least one of redundant logic circuitry and redundant memory locations. 
   
   
       5 . The apparatus of  claim 1 , further comprising test circuitry in at least one of the integrated circuits of the first stacked integrated circuit, wherein the test circuitry provides at least one of circuit testing before the first stacked integrated circuit is completed and after the first stacked integrated circuit is completed. 
   
   
       6 . The apparatus of  claim 1 , wherein at least one of the integrated circuits of the first stacked integrated circuit has a thickness of less than 50 microns. 
   
   
       7 . The apparatus of  claim 1 , wherein at least one of the integrated circuits of the first stacked integrated circuit is a thinned substantially flexible integrated circuit, formed with a low stress dielectric, wherein the low stress dielectric is at least one of an oxide of silicon and a nitride of silicon and is caused to have a tensile stress of about 5×10 8  dynes/cm 2  or less. 
   
   
       8 . The apparatus of  claim 1 , wherein at least two of the plurality of integrated circuits of the first stacked integrated circuit are bonded together by means of a patterned metal bond layer. 
   
   
       9 . The apparatus of  claim 1 , wherein the plurality of integrated circuits of the first stacked integrated circuit comprise means for performing a plurality of uniquely initiated concurrent information transfers on distinct transmission paths. 
   
   
       10 . The apparatus of  claim 1 , further comprising vertical interconnects interconnecting a plurality of integrated circuits of the first stacked integrated circuit, the vertical interconnects comprising vertical interconnect segments formed of a first metal contact on a first substrate bonded to a second aligned metal contact on a second adjacent substrate. 
   
   
       11 . The apparatus of  claim 1 , further comprising a substantially rigid substrate supporting at least one of the plurality of integrated circuits of the first stacked integrated circuit, the substantially rigid substrate having a first thickness, wherein at least one of the integrated circuits of the first stacked integrated circuit has a second thickness, wherein the second thickness is substantially less than the first thickness. 
   
   
       12 . The apparatus of  claim 1 , wherein at least one of the integrated circuits of the first stacked integrated circuit is fabricated with at least one of a different semiconductor process technology and a different geometric process fabrication technology than at least one of the other integrated circuits of the first stacked integrated circuit. 
   
   
       13 . A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:
 a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of memory integrated circuits of at least one integrated circuit type;   wherein the second stacked integrated circuit comprises at least one memory integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more memory integrated circuit of said integrated circuit type than said second stacked integrated circuit, the memory integrated circuits of said integrated circuit type within the first stacked integrated circuit being of substantially the same design as the memory integrated circuits of said integrated circuit type within the second stacked integrated circuit.   
   
   
       14 . The apparatus of  claim 13 , wherein the integrated circuits of said integrated circuit type within the first stacked integrated circuit being of identical design as the integrated circuits of said integrated circuit type within the second stacked integrated circuit. 
   
   
       15 . A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:
 a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of integrated circuits of at least one integrated circuit type;   wherein the second stacked integrated circuit comprises at least one integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more integrated circuit of said integrated circuit type than said second stacked integrated circuit, wherein a design of the integrated circuits of said integrated circuit type within the first stacked integrated circuit and a design of the integrated circuits of said integrated circuit type within the second stacked integrated circuit are the same or are derived from the same integrated circuit design.   
   
   
       16 . A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:
 a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of integrated circuits of at least one integrated circuit type;   wherein the second stacked integrated circuit comprises at least one memory integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more integrated circuit of said integrated circuit type than said second stacked integrated circuit, wherein a design of the memory integrated circuits of said integrated circuit type within the first stacked integrated circuit and a design of the memory integrated circuits of said integrated circuit type within the second stacked integrated circuit are the same or are derived from the same integrated circuit design.   
   
   
       17 . A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:
 a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of integrated circuits of at least one integrated circuit type;   wherein the second stacked integrated circuit comprises at least one integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more integrated circuit of said integrated circuit type than said second stacked integrated circuit, the integrated circuits of said integrated circuit type within the first stacked integrated circuit being functionally equivalent to the integrated circuits of said integrated circuit type within the second stacked integrated circuit.   
   
   
       18 . A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:
 a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of memory integrated circuits of at least one integrated circuit type;   wherein the second stacked integrated circuit comprises at least one memory integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more memory integrated circuit of said integrated circuit type than said second stacked integrated circuit, the memory integrated circuits of said integrated circuit type within the first stacked integrated circuit being functionally equivalent to the memory integrated circuits of said integrated circuit type within the second stacked integrated circuit.   
   
   
       19 . A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:
 a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of integrated circuits of at least one integrated circuit type;   wherein the second stacked integrated circuit comprises at least one integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more integrated circuit of said integrated circuit type than said second stacked integrated circuit.   
   
   
       20 . A first stacked integrated circuit related to a second stacked integrated circuit, the first stacked integrated circuit comprising:
 a plurality of integrated circuits held in an unmovable relation to one another, including a plurality of memory integrated circuits of at least one integrated circuit type;   wherein the second stacked integrated circuit comprises at least one memory integrated circuit of said integrated circuit type, and said first stacked integrated circuit comprising at least one more memory integrated circuit of said integrated circuit type than said second stacked integrated circuit.