Semiconductor memory device and refresh period controlling method

Abstract

Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors.

1 . A semiconductor memory device comprising:
 a memory array including a plurality of memory cells, each of said memory cells being in need of a refresh operation for retention of data;   a circuit for writing preset data in predetermined plural memory cells, referred to as monitor cells, provided in said memory array;   a circuit for performing control for reading data from said plural monitor cells, in which said preset data have been written, with the lapse of time equal to or shorter than a refresh period;   a circuit for comparing the data read from said monitor cell with said preset data to measure an error count or an error rate and for variably controlling the refresh period based on a measured result of said error count or the error rate; and   an error correction decoder,   wherein   when the measured error count or error rate has exceeded the preset value as determined by said circuit for comparing the data read from said monitor cell with said preset data, error correction decoding for said memory array is carried out by said error correction decoder to lower the error rate to a desired value.   
   
   
       2 . The semiconductor memory device according to  claim 1 , wherein
 said memory cell includes:   a cell transistor having a terminal connected to a word line for being controlled on/off, said cell transistor having a first signal terminal connected to a bit line; and   a capacitor for storing data therein by having one end thereof connected to a second signal terminal of said cell transistor;   said preset data being of such a value as to cause electric charge to be stored in said capacitor in the selected memory cell.   
   
   
       3 . The semiconductor memory device according to  claim 1 , wherein
 said refresh is self-refresh; and wherein   said semiconductor memory device further comprises   a circuit for controlling said refresh period for said self-refresh so that said error count or error rate as measured during said self-refresh is within a desired setting range.   
   
   
       4 . The semiconductor memory device according to  claim 1 , wherein
 said refresh is self-refresh; and wherein   said semiconductor memory device further comprises:   an error correction circuit; and   a circuit for controlling said self-refresh period so that said error count or error rate as measured during said self-refresh is within a range correctable by said error correction circuit.   
   
   
       5 . The semiconductor memory device according to  claim 1 , further comprising
 a test control circuit for generating an internal command and an internal address for writing and reading of preset data for said monitor cells and for controlling the comparison of the read data with expected value data.   
   
   
       6 . The semiconductor memory device according to  claim 1 , wherein
 said plural monitor cells are provided in a monitor area provided separately from a usual memory area in said memory array.   
   
   
       7 . The semiconductor memory device according to  claim 6 , wherein
 said error count or said error rate is measured by said circuit for writing preset data in predetermined plural memory cells writing physical or logical data ‘1’ in the monitor cell of said monitor area and by said circuit for performing control for reading data from said plural cells reading said ‘1’ data from said monitor cell at a period equal to or shorter than said refresh period.   
   
   
       8 . The semiconductor memory device according to  claim 6 , wherein
 said monitor area has an unused area of a redundancy restoration memory.   
   
   
       9 . The semiconductor memory device according to  claim 6 , wherein
 said monitor area includes, as said monitor cells, the memory cells connected to one or more word lines and selected by said word line distinct from word lines provided in a usual memory area in said memory array.   
   
   
       10 . The semiconductor memory device according to  claim 1 , wherein
 said monitor cell is a memory cell of an optional address in said memory array;   there being provided a memory device having stored therein an internal address of said monitor cell; and wherein   said monitor cell is accessed by the internal address from said memory device during writing and read of data for said monitor cell.   
   
   
       11 . The semiconductor memory device according to  claim 1 , further comprising:
 an ECC (error-checking and correction) encoding/decoding circuit for performing error checking and correction of data stored in said memory array;   wherein   data of said memory array is read at the time of entry to a data retention operation mode, said error detection correction encoding/decoding circuit generating check bits for error detection and correction for storage in a preset check area of said memory array;   said circuit for comparing the data read from said monitor cell with said preset data setting said refresh period to a longer value within the range allowed for error generation by an error correction operation employing check bits;   said error detection correction encoding/decoding circuit performing an error bit correction and decoding of said memory array, using said check bits, by said error detection correction encoding/decoding circuit, before reversion to the normal operation in exiting from the data retention mode.   
   
   
       12 . The semiconductor memory device according to  claim 1 , further comprising:
 an ECC (error-checking and correction) encoding/decoding circuit for performing error checking and correction of data stored in said memory array;   wherein data of said memory array is read at the time of entry to a data retention operation mode;   said error detection correction encoding/decoding circuit generates check bits for error detection and correction and stores the check bits generated in a preset check area of said memory array;   (A1) an expected value data ‘1’ is written in said monitor cell by said circuit for writing preset data in predetermined plural memory cells;   (A2) all cells of said memory array are refreshed by a refresh circuit connected to said memory array;   (A3) the operation is paused during the refresh time by said refresh circuit;   (A4) data is read from said monitor cell by said circuit for performing control for reading data, and compared with the expected value data ‘1’ by said circuit for comparing the data read from said monitor circuit with said preset data to measure an error; and   (A5) when said error rate is larger than a preset upper limit value, the refresh period is shortened by said circuit for comparing the data read from said monitor circuit with said preset data, when said error rate is not larger than a preset lower limit value, the refresh period is elongated by said circuit for comparing the data read from said monitor circuit with said preset data and, when said error rate is intermediate between said preset upper and lower limit values, the refresh period is not changed by said circuit for comparing the data read from said monitor circuit with said preset data;   the operations from (A1) to (A5) are repeated until exiting from said data retention mode; and wherein   when exiting from the data retention mode, error correction is carried out in said error detection correction encoding/decoding circuit before proceeding to the normal operation.   
   
   
       13 . The semiconductor memory device according to  claim 1 , further comprising:
 an ECC (error-checking and correction) encoding/decoding circuit for performing error checking and correction of data stored in said memory array;   wherein data of said memory array is read at the time of entry to a data retention mode,   said ECC encoding/decoding circuit generates check bits for error detection and correction for storage in a preset check area of said memory array;   (A1) an expected value data ‘1’ is written in said monitor cell by said circuit for writing preset data in predetermined plural memory cells;   (A2) all cells of said memory array are refreshed by a refresh circuit connected to said memory array, the pause period is made shorter than the refresh period and not larger than a preset number (m) times of error check operations are carried out; that is,   (A3) at least a part of the internal power supply is turned off by a timer to make a pause for a preset pause period;   (A4) data is read from said monitor cell by said circuit for performing control for reading data, and compared with the expected value data ‘1’ by said circuit for comparing the data read from said monitor circuit with said preset data to measure an error;   (A5) when said error rate is larger than a preset upper limit value, the refresh period is shortened by said circuit for comparing the data read from said monitor circuit with said preset data and, when said error rate is intermediate between said preset upper and lower limit values, the refresh period is not changed by said circuit for comparing the data read from said monitor circuit with said preset data and the processing as from (A 1 ) is commenced; and   (A6) if, after m times of the error check operations, said error rate is not larger than a preset lower limit value, the refresh period is elongated by said circuit for comparing the data read from said monitor circuit with said preset data; wherein the operations of (A1) until A(6) are repeated until exiting from the data retention mode; and wherein   when exiting from the data retention mode, error correction is carried out in said ECC encoding/decoding circuit before proceeding to the normal operation.   
   
   
       14 . The semiconductor memory device according to  claim 1 , further comprising:
 an ECC (error-checking and correction) encoding/decoding circuit for performing error checking and correction of data stored in said memory array; wherein data of said memory array is read at the time of entry to a data retention mode, said ECC encoding/decoding circuit generating check bits for error detection and correction for storage in a preset check area of said memory array;   (A1) all cells of said memory array are refreshed by a refresh circuit and the pause period is made shorter than the refresh period;   (A2) it is checked by said ECC encoding/decoding circuit whether or not an error check has been carried out a preset number (m) of times;   if the number of times is less than m, then   (A3) all cells of said memory array are refreshed by said refresh circuit;   (A4) pause is made during the pause period by said refresh circuit, based on a timer value provided by a timer circuit;   (A5) data is read from said monitor cell by said circuit for performing control for reading data, and compared with the expected value data ‘1’ by said circuit for comparing the data read from said monitor circuit with said preset data to measure an error;   (A6) when said error rate is larger than a preset upper limit value, the refresh period is shortened by said circuit for comparing the data read from said monitor circuit with said preset data, when said error rate is intermediate between said preset upper and lower limit values, the refresh period is not changed by said circuit for comparing the data read from said monitor circuit with said preset data and, when said error rate is not larger than a preset lower limit value, the refresh period is elongated by said circuit for comparing the data read from said monitor circuit with said preset data and the processing as from (A2) is started;   after the end of m times of the error check, the processing as from (A1) above is performed;   the operations of (A1) until A(6) are repeated until exiting from the data retention mode; and wherein   when exiting from the data retention mode, error correction is carried out in said ECC encoding/decoding circuit before proceeding to the normal operation.   
   
   
       15 . The semiconductor memory device according to  claim 1 , further comprising:
 an ECC (error-checking and correction) encoding/decoding circuit for performing error checking and correction of data stored in said memory array; wherein data of said memory array is read at the time of entry to a data retention mode, said ECC encoding/decoding circuit generating check bits for error detection and correction for storage in a check area of said memory array;   (A1) an expected value data ‘1’ is written in said monitor cell by said circuit for writing preset data in predetermined plural memory cells;   (A2) all cells of said memory array are refreshed by a refresh circuit; the pause period is made shorter than a refresh period;   (A3) it is judged whether or not by said ECC encoding/decoding circuit whether error check has been carried out a preset number (m) of times;   if the number of times is less than m,   (A4) a pause is made for a preset pause period by said refresh circuit, based on a timer value provided by a timer circuit;   (A5) data is read from said monitor cell by said circuit for performing control for reading data, and compared with the expected value data ‘1’ by said circuit for comparing the data read from said monitor circuit with said preset data to measure an error;   (A6) when said error rate is larger than a preset upper limit value, the refresh period is shortened by said circuit for comparing the data read from said monitor circuit with said preset data, when said error rate is intermediate between said preset upper and lower limit values, the refresh period is not changed by said circuit for comparing the data read from said monitor circuit with said preset data; when said error rate is not larger than a preset lower limit value, the refresh period is elongated by said circuit for comparing the data read from said monitor circuit with said preset data and the processing as from (A3) is commenced;   the processing as from (A1) is carried out after the end of m times of error check operations;   the operations of (A1) until A(6) are repeated until exiting from the data retention mode; and wherein   when exiting from the data retention mode, error correction is carried out in said ECC encoding/decoding circuit before proceeding to the normal operation.   
   
   
       16 . The semiconductor memory device according to  claim 1 , wherein
 plural storage locations of said memory array inferior in the capability of the pause refresh to the usual memory area are used as said monitor cell.   
   
   
       17 . The semiconductor memory device according to  claim 16 , wherein
 storage locations of said memory array inferior in the capability of the pause refresh than the usual memory area are those bits obtained on carrying out bit restoration by pause refresh for a preset number (M) of bits and selecting approximately one-tenth of said preset number M of bits of the worst capability.   
   
   
       18 . The semiconductor memory device according to  claim 1 , wherein said an error correction decoder comprises:
 a plurality of half-adder circuits;   a plurality of 2-bits adder circuits configured to receive outputs from a respective pair of said plurality of half-adder circuits; and   a plurality of 3-bits adder circuits configured to receive outputs from a respective pair of said plurality of 2-bits adder circuits.