System And Method of Coherent Data Transfer During Processor Idle States

Abstract

Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.

1 - 27 . (canceled) 
   
   
       28 . A method comprising:
 determining, by detecting a request, whether a processor has flushed an internal cache of the processor to a system memory prior to placing the processor in a non-snoopable idle state; and   in response to the request, placing the processor in the non-snoopable idle state, the processor being associated with the system memory of a computer system.   
   
   
       29 . The method of  claim 28 , further comprising:
 servicing a data transfer between the system memory and a controller while the processor is in the non-snoopable idle state; and   removing the processor from the non-snoopable idle state upon detecting a wake-up event.   
   
   
       30 . The method of  claim 28 , wherein the request comprises an input/output read request from the processor to read from a particular register. 
   
   
       31 . The method of  claim 29 , wherein servicing includes:
 detecting a bus master request from a memory controller hub; and   moving data between the system memory and the memory controller hub based on the bus master request.   
   
   
       32 . The method of  claim 29 , wherein the servicing includes:
 detecting a bus master request from a peripheral controller; and   moving data between the system memory and the peripheral controller based on the bus master request.   
   
   
       33 . The method of  claim 29 , wherein the servicing includes:
 detecting a bus master request from an input/output controller hub; and   moving data between the system memory and the input/output controller hub based on the bus master request.   
   
   
       34 . A apparatus comprising:
 an integration circuit including:   a power management logic to
 determine, by detecting a request, whether a processor has flushed an internal cache of the processor to a system memory prior to placing the processor in a non-snoopable idle state; and 
 in response to the request, place the processor in the non-snoopable idle state, the processor being associated with the system memory of a computer system; and 
   a non-snoop mode logic to service a data transfer between the system memory and a controller while the processor is in the non-snoopable idle state.   
   
   
       35 . The apparatus of  claim 34 , wherein the power management logic is modified to:
 service a data transfer between the system memory and a controller while the processor is in the non-snoopable idle state; and   remove the processor from the non-snoopable idle state upon detecting a wake-up event.   
   
   
       36 . The apparatus of  claim 34 , wherein the request comprises an input/output read request from the processor to read from a particular register. 
   
   
       37 . The apparatus of  claim 35 , wherein power management logic is further modified to:
 detect a bus master request from a memory controller hub; and   move data between the system memory and the memory controller hub based on the bus master request.   
   
   
       38 . The apparatus of  claim 35 , wherein power management logic is further modified to:
 detect a bus master request from a peripheral controller; and   move data between the system memory and the peripheral controller based on the bus master request.   
   
   
       39 . The apparatus of  claim 35 , wherein power management logic is further modified to:
 detect a bus master request from an input/output controller hub; and   move data between the system memory and the input/output controller hub based on the bus master request.   
   
   
       40 . A system comprising:
 a computer system including a processor coupled with a system memory, the processor having   an input/output controller hub (ICH) having a power management logic to
 determine, by detecting a request, whether a processor has flushed an internal cache of the processor to a system memory prior to placing the processor in a non-snoopable idle state; and 
 in response to the request, place the processor in the non-snoopable idle state, the processor being associated with the system memory of a computer system; and 
   a memory controller hub (MCH) coupled with the ICH, the MCH having a non-snoop mode logic to service a data transfer between the system memory and a controller while the processor is in the non-snoopable idle state.   
   
   
       41 . The system of  claim 40 , wherein the power management logic is modified to:
 service a data transfer between the system memory and a controller while the processor is in the non-snoopable idle state; and   remove the processor from the non-snoopable idle state upon detecting a wake-up event.   
   
   
       42 . The system of  claim 40 , wherein the request comprises an input/output read request from the processor to read from a particular register. 
   
   
       43 . The system of  claim 41 , wherein power management logic is further modified to:
 detect a bus master request from a memory controller hub; and   move data between the system memory and the memory controller hub based on the bus master request.   
   
   
       44 . The system of  claim 41 , wherein power management logic is further modified to:
 detect a bus master request from a peripheral controller; and   move data between the system memory and the peripheral controller based on the bus master request.   
   
   
       45 . The system of  claim 41 , wherein power management logic is further modified to:
 detect a bus master request from an input/output controller hub; and   move data between the system memory and the input/output controller hub based on the bus master request.