Flash memory having a high-permittivity tunnel dielectric

Abstract

A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be deposited using evaporation techniques or atomic layer deposition techniques. The floating gate is formed on top of the high-k dielectric layer with an oxide gate insulator on top of that. A polysilicon control gate is formed on the top gate insulator.

1 . A method for fabricating a flash memory cell, the method comprising:
 creating a plurality of source/drain regions by doping portions of a substrate;   forming an atomic layer deposition (ALD) tunnel dielectric layer with an atomic layer deposition technique on the substrate substantially between the plurality of source/drain regions, the ALD tunnel dielectric layer having a dielectric constant that is higher than silicon dioxide;   depositing a floating gate on the evaporated tunnel dielectric layer;   depositing an oxide insulator material on the floating gate; and   forming a control gate on the oxide insulator material.   
   
   
       2 . The method of  claim 1  wherein forming an ALD tunnel gate insulator comprises depositing one of AlO X , LaAlO 3 , HfAlO 3 , Pr 2 O 3 , Lanthanide-doped TiO x , HfSiON, Zr—Sn—Ti—O films using TiCl 4  or TiI 4 , ZrON, HfO 2 /Hf, ZrAlXO y , CrTiO 3 , or ZrTiO 4 . 
   
   
       3 . A method for fabricating a memory device on a substrate, the memory device having a plurality of memory cells, the method comprising:
 doping a source region and a drain region into the substrate for each memory cell;   forming a tunnel dielectric layer over the substrate substantially between each pair of source and drain regions, each tunnel dielectric layer having a barrier height that is less than silicon dioxide;   forming a floating gate over each tunnel dielectric layer;   forming a gate insulator over each floating gate; and   forming a gate over each gate insulator.   
   
   
       4 . The method of  claim 3  wherein the tunnel dielectric layer comprises a high permittivity gate dielectric. 
   
   
       5 . The method of  claim 4  wherein the tunnel dielectric layer has a band gap of 6.6 eV and a conduction band offset of 2.1 eV. 
   
   
       6 . The method of  claim 3  wherein the tunnel dielectric layer is formed using atomic layer deposition using sequential deposition of individual monolayers or fractions of a monolayer where gaseous precursors are introduced one at a time to the substrate. 
   
   
       7 . The method of  claim 3  wherein the floating gate comprises a polysilicon layer. 
   
   
       8 . The method of  claim 3  wherein the gate insulator comprises an interpoly oxide insulator layer. 
   
   
       9 . The method of  claim 3  wherein the tunnel dielectric layer is less than 15 Å thick. 
   
   
       10 . A method for fabricating a memory device, the method comprising:
 forming a pair of source/drain regions in the substrate for each memory cell of the memory device;   forming a tunnel dielectric with atomic layer deposition, using an oxygen source of one of hydrogen peroxide, ozone, or nitrous oxide, over the substrate and substantially between each pair of source/drain regions, each tunnel dielectric layer having a barrier height that is less than silicon dioxide and is comprised of a metal compound;   forming a floating gate over each tunnel dielectric;   forming a gate insulator over each floating gate; and   forming a gate over each gate insulator.   
   
   
       11 . The method of  claim 10  wherein the tunnel dielectric is formed by a plurality of reaction steps, including a first precursor that is saturatively chemisorbed at the substrate surface, in a flow-type reactor. 
   
   
       12 . The method of  claim 11  and further including purging the first precursor and introducing a second precursor that is introduced on the substrate for films growth reaction. 
   
   
       13 . The method of  claim 12  and further including purging byproducts and the second precursor. 
   
   
       14 . The method of  claim 10  wherein the tunnel dielectric is formed from one of source materials: zirconium tetrachloride (ZrCl 4 ) for a Zr film, titanium tetraisopropoxide (Ti(OCH(CH 3 ) 2 ) 4 ) for a Ti film, trimethyl aluminum (Al(CH 3 ) 3 ) for an Al film, chromyl chromide (CrO 2 Cl 2 ) for a Cr film, praseodymium chloride (PrCl 3 ) for a Pr film, and hafnium chloride (HfCl 4 ) for an Hf film. 
   
   
       15 . The method of  claim 14  wherein thin oxide films are deposited on the substrate at a temperature that is high enough such that it is absorbed to the substrate surface. 
   
   
       16 . The method of  claim 15  wherein vaporized source material reacts with a molecular layer of a second source material. 
   
   
       17 . The method of  claim 16  wherein the vaporized source material becomes absorbed and reacts with the second source material directed to the substrate surface in a subsequent fabrication step. 
   
   
       18 . The method of  claim 10  wherein each memory cell is scaled below 50 nm. 
   
   
       19 . The method of  claim 10  wherein the oxygen sources further comprise water and alcohols. 
   
   
       20 . The method of  claim 10  wherein tunnel dielectric materials include one of Si 3 N 4 , Al 2 O 3 , Y 2 O 3 , La 2 O 3 , Ta 2 O 3 , TiO 2 , HfO 2 , ZrO 2 .