Advanced receiver with sliding window block linear equalizer
Abstract
A receiver or an integrated circuit (IC) incorporated therein includes a fast Fourier transform (FFT)-based (or hybrid FFT-based) sliding window block level equalizer (BLE) for generating equalized samples. The BLE includes a noise power estimator, first and second channel estimators, an FFT-based chip level equalizer (CLEQ) and a channel monitor unit. The noise power estimator generates a noise power estimate based on two diverse sample data streams. The channel estimators generate respective channel estimates based on the sample data streams. The channel monitor unit generates a first channel monitor signal including truncated channel estimate vectors based on the channel estimates, and a second channel monitor signal which indicates an approximate rate of change of the truncated channel estimate vectors. The FFT-based CLEQ generates the equalized samples based on the noise power estimate, one-block samples of the first and second sample data streams, the channel estimates and the monitor signals.
Claims
exact text as granted — not AI-modified1 . A method for generating equalized samples in a receiver, the method comprising:
receiving a first and second sample data stream; receiving even and odd samples associated with the first sample data stream; receiving even and odd samples associated with the second sample data stream; generating a noise power estimate based on odd and even samples associated with each of the first and second sample data streams; and generating equalized samples based on the noise power estimate and one-block samples of the first and second sample data streams.
2 . The method of claim 1 further comprising:
generating a first channel estimate based on the first sample data stream; and generating a second channel estimate based on the second sample data stream, wherein equalized samples are further based on the first and second channel estimates.
3 . The method of claim 2 further comprising:
generating a first channel monitor signal including truncated channel estimate vectors based on the first and second channel estimates, and a second channel monitor signal which indicates an approximate rate of change of the truncated channel estimate vectors included in the first channel monitor signal.
4 . A method for generating equalized samples in a receiver comprising:
generating a noise power estimate based on odd and even samples associated with a first sample data stream and a second sample data stream; generating an even sample channel estimate based on the even samples in the first sample data stream; generating an odd sample channel estimate based on the odd samples in the second sample data stream; generating equalized samples comprising:
receiving the even sample channel estimate;
receiving the odd sample channel estimate;
receiving the noise power estimate;
outputting a first hybrid fast Fourier transform (FFT) output signal; and
outputting a second hybrid FFT output signal;
generating final tap filter coefficients associated with the even samples;
generating final tap filter coefficients associated with the odd samples;
performing time domain equalization on the even samples using the final tap filter coefficients associated with the even samples to generate a first equalized signal;
performing time domain equalization on the odd samples using the final tap filter coefficients associated with the odd samples to generate a second equalized signal; and
adding the first and second equalized signals together to generate the equalized samples.
5 . The method of claim 4 further comprising:
performing at least one of truncation, noise filtering and tap coefficient reordering.
6 . The method of claim 4 further comprising:
generating a first zero-padded signal by performing zero padding on the even sample channel estimate; generating a second zero-padded signal by performing zero padding on the odd sample channel estimate; generating a first FFT-processed signal by performing an FFT operation on the first zero-padded signal; generating a second FFT-processed signal by performing an FFT operation on the second zero-padded signal; generating a first complex conjugate signal by performing a complex conjugate operation on the first FFT-processed signal; generating a second complex conjugate signal by performing a complex conjugate operation on the second FFT-processed signal; generating a first product result signal by multiplying the first FFT-processed signal with the first complex conjugate signal; generating a second product result signal by multiplying the second FFT-processed signal with the second complex conjugate signal; generating a first summed signal by adding the first and second product result signals; generating a second summed signal by adding the first summed signal and the noise power estimate to generate a second summed signal; generating a first quotient result signal by dividing the first complex conjugate signal by the second summed signal; generating a second quotient result signal by dividing the second complex conjugate signal by the second summed signal; generating the first hybrid FFT output signal by performing an IFFT operation on the first quotient result signal; and generating the second hybrid FFT output signal by performing an IFFT operation on the second quotient result signal.Join the waitlist — get patent alerts
Track US2009190645A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.