Increasing workload performance of one or more cores on multiple core processors

Abstract

A processing node that is integrated onto a single integrated circuit chip includes a first processor core and a second processor core. The processing node also includes an operating system executing on either of the first processor core and the second processor core. The operating system may monitor a current utilization of the first processor core and the second processor core. The operating system may cause the first processor core to operate at performance level that is lower than a system maximum performance level and the second processor core to operate at performance level that is higher than the system maximum performance level in response to detecting the first processor core operating below a utilization threshold.

1 - 15 . (canceled) 
   
   
       16 . A processing node comprising, integrated onto a single integrated circuit chip:
 a first processor core;   a second processor core;   an operating system executing on either of the first processor core and the second processor core is configured to independently control a performance level of each of the first processor core and the second processor core dependent upon a current utilization level of either of the first processor core and the second processor core.   
   
   
       17 . The processing node as recited in  claim 16 , wherein in response to detecting a reduction in the current utilization level of the first processor core, the operating system is configured to decrease the performance level of the first processor core and to increase the performance level of the second processor core by a corresponding amount above a system maximum performance level. 
   
   
       18 . The processing node as recited in  claim 16 , wherein in response to detecting a reduction in the current utilization level of the second processor core, the operating system is configured to decrease the performance level of the second processor core and to increase the performance level of the first processor core by a corresponding amount above a system maximum performance level. 
   
   
       19 . The processing node as recited in  claim 16 , wherein in response to detecting a reduction in the current utilization level of the first processor core below a minimum utilization level, the operating system is configured to place the first processor core in a minimum power state and to increase the performance level of the second processor core to a core maximum performance level. 
   
   
       20 . A method comprising:
 a first processor core executing instructions;   a second processor core executing instructions;   an operating system executing on either of the first processor core and the second processor core and independently controlling a performance level of each of the first processor core and the second processor core dependent upon a current utilization level of either of the first processor core and the second processor core.   
   
   
       21 . The method as recited in  claim 20 , wherein in response to detecting a reduction in the current utilization level of the first processor core, the operating system decreasing the performance level of the first processor core and increasing the performance level of the second processor core by a corresponding amount above a system maximum performance level. 
   
   
       22 . The method as recited in  claim 20 , wherein in response to detecting a reduction in the current utilization level of the second processor core, the operating system decreasing the performance level of the second processor core and increasing the performance level of the first processor core by a corresponding amount above a system maximum performance level. 
   
   
       23 . The method as recited in  claim 20 , wherein in response to detecting a reduction in the current utilization level of the first processor core below a minimum utilization level, the operating system placing the first processor core in a minimum power state and increasing the performance level of the second processor core to a core maximum performance level.