De-emphasis system and method for coupling digital signals through capacitively loaded lines

Abstract

A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

1 . (canceled) 
   
   
       2 - 34 . (canceled) 
   
   
       35 . A processor-based system, comprising
 a system processor having a processor bus;   a system memory operable to store write data and to retrieve read data at locations corresponding received address signals responsive to memory commands; and   a system controller coupled to the system processor through the processor bus, the system controller being coupled to the system memory and being operable to supply to the system memory a memory signal corresponding to either a first logic level or a second logic level, the system controller including a de-emphasis system configured to de-emphasize the memory signal before transmitting the memory signal to the system memory, the de-emphasis system having an input coupled to receive the memory signal and being configured to generate a de-emphasized memory signal that is supplied to the system memory, the de-emphasized memory signal corresponding to a transition from the first logic level to the second logic level having a first signal level for a first period followed by a second signal level for as long as the memory signal corresponds to the second logic level.   
   
   
       36 . The processor-based system of  claim 35  wherein the de-emphasized memory signal comprises a de-emphasized address signal. 
   
   
       37 . The processor-based system of  claim 35  wherein the de-emphasized memory signal comprises a de-emphasized command signal. 
   
   
       38 . The processor-based system of  claim 35  wherein the de-emphasis system is further configured to generate a de-emphasized memory signal that corresponds to a transition from the second logic level to the first logic level having a third signal level for a second period followed by a fourth signal level for as long as the memory signal corresponds to the first logic level. 
   
   
       39 . The processor-based system of  claim 38  wherein the first and second periods are substantially equal to each other. 
   
   
       40 . The processor-based system of  claim 39  wherein the de-emphasis system comprises:
 a delay circuit receiving a digital signal having either the first logic level or the second logic level and being configured to generate a delayed memory signal at an output terminal having a delay relative to the memory signal that is equal to the first period responsive to a transition of the digital signal from the first logic level to the second logic level and is equal to a second period responsive to a transition of the digital signal from the second logic level to the first logic level;   a first multiplier circuit that is operable to generate a first intermediate signal by multiplying the magnitude of the delayed memory signal by a first multiplier,   a second multiplier circuit that is operable to generate second intermediate signals by multiplying the magnitude of the delayed memory signal by a second multiplier; and   a combining circuit coupled to receive the first and second intermediate signals to generate de-emphasized memory signal for transmission to the system memory by combining the first and second intermediate signals.   
   
   
       41 . The processor-based system of  claim 40  wherein the first multiplier comprises 1-X and the second multiplier comprises X where X is a value less than 1. 
   
   
       42 . The processor-based system of  claim 40  wherein the memory signal is synchronized to a clock signal, and wherein the first and second delays are substantially equal to one period of the clock signal. 
   
   
       43 . The processor-based system of  claim 38  wherein the magnitude of the third signal level is substantially equal to the magnitude of the first logic level. 
   
   
       44 . The processor-based system of  claim 38  wherein the duration of the first period is equal to the duration of the second period. 
   
   
       45 . The processor-based system of  claim 38  wherein the magnitude of the third signal level is substantially equal to the magnitude of the first logic level, and wherein the magnitude of the first signal level is substantially equal to the magnitude of the second logic level. 
   
   
       46 . The processor-based system of  claim 38  wherein the magnitudes of the second and fourth signal levels are intermediate the magnitudes of the first and third signal levels. 
   
   
       47 . The processor-based system of  claim 38  wherein the magnitude of the first signal level is substantially equal to the magnitude of the second logic level. 
   
   
       48 . A processor-based system, comprising
 a system processor having a processor bus;   a system memory operable to store write data and to retrieve read data at locations corresponding received address signals responsive to memory commands; and   a system controller coupled to the system processor through the processor bus, the system controller being coupled to the system memory and including a de-emphasis system configured to generate a de-emphasized memory signal corresponding to a digital signal having first and second logic level and to transmit the de-emphasized memory signal to the system memory, the de-emphasis system being responsive to the digital signal transitioning from the first logic level to the second logic level to cause the de-emphasized memory signal to initially overshoot a first signal level and then remain at the first signal level for as long as the digital signal is at the second logic level.   
   
   
       49 . The processor-based system of  claim 48  wherein the de-emphasis system is further responsive to the digital signal transitioning from the second logic level to the first logic level to cause the de-emphasized memory signal to initially overshoot a second signal level and then remain at the second signal level for as long as the digital signal is at the first logic level. 
   
   
       50 . The processor-based system of  claim 49  wherein the magnitude of the second signal level is substantially equal to the magnitude of the first logic level. 
   
   
       51 . The processor-based system of  claim 49  wherein the de-emphasized signal overshoots the first signal level for a first period and overshoots the second signal level for a second period that is substantially equal to the first period. 
   
   
       52 . The processor-based system of  claim 48  wherein the magnitude of the first signal level is substantially equal to the magnitude of the second logic level. 
   
   
       53 . The processor-based system of  claim 48  wherein the de-emphasized signal overshoots the first signal level for a first period. 
   
   
       54 . The processor-based system of  claim 48  wherein the de-emphasized memory signal comprises a de-emphasized address signal.