Layout method for soft-error hard electronics, and radiation hardened logic cell

Abstract

This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modem technologies (≦90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors.

1 . A method for laying out an electronic circuit wherein the electronic circuit comprises contact areas, said method comprising:
 a. determining the effect on the voltage state of one or more nets in the circuit, due to a single event occurring near each contact area, for each contact area in the circuit;   b. categorizing the contact areas in such a way that contact areas for which a single event have opposing effects on the voltage state of the nets in the circuit, and for which a single event has a non-opposing effect on the voltage state of the nets in the circuit, are identified;   c. placing these contact areas in such a way that when a single event has opposing effects on the voltage state of the circuit nets, the opposing first and second contact areas are placed as close to each other as permitted by the circuit and by the design rules;   d. placing a first contact area and a second contact area, with non-opposing effects on the voltage state of the nets in the circuit, said non-opposing effects caused by a single event, wherein the first and second contact areas are non-adjoining, and placing a third contact area in between the first and second contact areas, wherein said third contact area has an effect on the voltage state of the nets in the circuit opposing those of the first and second contact areas, and wherein the third contact area's effect on the voltage state of the nets in the circuit is caused by a single event, and   e. adjusting the strength of the effect of a single event on the placed contact areas in such a way that the opposing effects are of the same, but opposite, strength.   
     
     
         2 . The method of claim ( 1 ), wherein the circuit has at least two nets carrying the same signal (or the signal and its' inverse), where each of these nets have at least two contact areas for which a single event has an opposing effect on the voltage state of said two nets, comprising:
 a. placing a first contact area and a second contact area, each from a separate redundant net, for which a single event has the effect of changing the voltage state on the two redundant nets, wherein the first and second contact areas are non-adjoining, and placing a third contact area in between the first and second contact areas, said third contact area having an effect on the voltage state on at least one of the redundant nets, and wherein said effect of the third contact area is caused by a single event and opposes the effects of the first and second contact areas, and   b. adjusting the strength of the effect of a single event on the placed contact areas in such a way that any single event that affects (passes through) the two redundant nets, at maximum can change the state of one of the nets, but never both nets.   
     
     
         3 . The method of  claim 1  or  2 , wherein the circuit utilizes MOSFET devices, further comprising:
 a. identifying all MOSFET source (S) and drain (D) doping areas, which are not directly connected to the power-nets (VSS,VDD) as the contact areas of claim (1) and (2); and   b. identifying the n-type MOSFET drains or sources, as contact areas for which a single event have the effect of pulling the voltage state, of the nets connected to this contact area, low, and the p-type MOSFET drains or sources, as contact areas for which a single event have the effect of pulling the voltage state, of the nets connected to this contact area, high.   
     
     
         4 . The method of  claim 3 , further comprising:
 a. adding additional MOSFET devices between two nets, which at any time, carry opposite voltage states (high/low voltage level), in such a way that if one (first) of the nets is affected by a single event, such that its' voltage state is changed, then the additional MOSFET device turns on, connecting the two nets, and hence ensures that the state of the second net is not changed; and   b. connecting the sources or drains of the p-type MOSFETs in the two nets by additional p-type MOSFETs with their gates connected to the high level power net (VDD), and connecting the sources or drains of the n-type MOSFETs in the two nets by additional n-type MOSFETs with their gates connected to the low level power net (VSS).   
     
     
         5 . A sequential logic or memory cell and layout, which uses two or more latches to store the state of the element, each latch having at least one net that stores the voltage state and at least one net that stores the opposite value (inverse) of the voltage state, comprising:
 a. an arrangement of the contact areas of each net (which keep a certain voltage state or its' inverse), in the such a way that the contacts areas of at least 4 of these nets are positioned symmetrically along one line in the layout, and positioned relative to each other such that no two contact areas, which:
 i. carry the same voltage state, and for which a single event have the same effect on the voltage state of the net; or 
 ii. carry different voltage states (i.e., a certain state and its' inverse), and for which a single event have opposite effect on the data (voltage) of the net are placed next to each other. 
   
     
     
         6 . A sequential logic cell, which consist of four inverter circuits, each inverter circuit consisting of one p-type MOSFET and one n-type MOSFET, where the inverters have been connected as a Dual Interlocked Cell (DICE) by connecting the outputs of each inverter to the gate of a p-type MOSFET of another, second, inverter, and to the gate of an n-type MOSFET of another third inverter, each gate being connected to one output only, and hence having four nets, one connected to each inverter output and to two gates, two nets carrying the same voltage state and the two other carrying the inverse of the voltage state of the first two nets, each net having one p-type drain contact area and one n-type drain contact area, comprising:
 a. An arrangement where the contact areas of each of the four nets, are placed along a line in the layout; and   b. In which two adjacent n-drain contact areas, or two adjacent p-drain contact areas, always belong to (are connected to) two nets which carry opposite voltage states, and where adjacent n-drain contact areas and p-drain contact areas always belong to nets that carry the same voltage state.   
     
     
         7 . The sequential Dual Interlocked Cell (DICE) circuit of claim ( 6 ), wherein one or more, additional protective MOSFET devices, are added and connected in between two circuit nets of the sequential element of  claim 6 , comprising:
 a. a configuration where said additional devices are connected such that additional p-type devices having their gates connected to the high voltage level (VDD), and either drain or source being (shared with) the p-type contact area of a first circuit net in the sequential circuit of  claim 6 , and the other contact (drain or source) either being connected to a source or drain contact area of another second additional p-type MOSFET, said second additional MOSFET having its' other contact (drain or source) being (shared with) the p-type contact area connected to a second net in the sequential circuit, or to a contact area which is adjacent to the p-type drain of the second net of the sequential circuit but not connect to a net, said second net in the sequential circuit having the inverse voltage state of the first net, and, additional n-type devices having their gates connected to the low voltage level (VSS), and either drain or source being (shared with) the n-type contact area of a first circuit net in the sequential circuit of  claim 6 , and the other contact (drain or source) either being connected to a source or drain contact area of another second additional n-type MOSFET, said second additional MOSFET having its' other contact (drain or source) being (shared with) the n-type contact area connected to a second net in the sequential circuit, or to a contact area which is adjacent to the n-type drain of the second net of the sequential circuit but not connect to a net, said second net in the sequential circuit having the inverse voltage state of the first net; and   b. a configuration where any additional drain or source contact areas belonging to the additional MOSFET devices are placed in the same line in the layout as the contact areas of the sequential circuit of  claim 6     
     
     
         8 . The sequential logic or memory cell and layout of claim ( 5 ), wherein a filtering or voting circuit is connected to the output of redundant nets, said filtering circuit, being used in the case of two redundant nets, preventing a data signal to pass unless both nets have the correct data, said voting circuit used on three redundant nets, performing a vote between the states of the redundant nets, comprising:
 a. a layout where the strength of the response to a single event have been adjusted such that the total effect, caused by a single event, on one of the nets (primary) is opposite to the total effect, caused by a single event, on its' redundant counterpart, ensuring that when a single event affects both the primary and redundant nets, one and only one, of these nets can change its state.   
     
     
         9 . A combinational circuit, where logic element have been duplicated (either throughout or in selected parts) and hence the data signal is carried by a primary net, and by a secondary net (carrying either the signal or it's inverse), and where either filtering circuits, preventing a signal to pass unless the two redundant nets carry the correct signal, have been place in front of each sequential elements, or the sequential elements also have been duplicated (the latter case requiring an error detection and/or correction at the end of the duplicated circuit chain), comprising:
 a. a layout where the contacts areas of two redundant nets (primary and secondary) are placed such that there is no straight line between a first and a second contact area, each from separate redundant nets, ad for which a single event has the effect of changing the voltage state in the net connected to the circuit area, unless there is, along this line, in between the first and second contact area, at least one third contacts area, for which a single event has an opposite effect, to that of the first and second contact areas, on the voltage state of at least one of the two redundant nets.   
     
     
         10 . The combinational circuit of  claim 9  comprising:
 a. a layout where the strength of the response to a single event have been adjusted such that the total effect, caused by a single event, on one of two redundant nets is opposite to the total effect, caused by a single event, on the other of the two redundant nets. ensuring that when a single event affects both of the two redundant nets, only one of these two nets can generate and error signal in the circuit.