High performance system-on-chip inductor using post passivation process

Abstract

A system and method for forming post passivation passive components, such as resistors and capacitors, is described. High quality electrical components, are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

1 . A system-on-chip structure comprising:
 a silicon substrate;   a metallization structure over said silicon substrate, wherein said metallization structure comprises a first interconnect layer over said silicon substrate and a second interconnect layer over said first interconnect layer;   a first dielectric layer between said first and second interconnect layers;   a passivation layer over said metallization structure and over said first dielectric layer, wherein said passivation layer comprises a nitride layer;   a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 150 micrometers and greater than that of said passivation layer; and   a capacitor on said polymer layer, wherein said capacitor comprises a lower plate on said polymer layer, an upper plate over said lower plate and a second dielectric layer between said upper and lower plates, wherein said lower plate has a thickness between 0.5 and 20 micrometers, said upper plate has a thickness between 0.5 and 20 micrometers, and said second dielectric layer has a thickness between 500 and 50,000 angstroms, wherein said lower plate comprises a first metal layer and a first electroplated copper layer on said first metal layer, and wherein said upper plate comprises a second metal layer and a second electroplated copper layer on said second metal layer.   
   
   
       2 . The system-on-chip structure of  claim 1 , wherein said second dielectric layer comprises a nitride. 
   
   
       3 . The system-on-chip structure of  claim 1 , wherein said second dielectric layer comprises titanium oxide. 
   
   
       4 . The system-on-chip structure of  claim 1 , wherein said second dielectric layer comprises tantalum oxide. 
   
   
       5 . The system-on-chip structure of  claim 1 , wherein said second dielectric layer comprises an oxide. 
   
   
       6 . The system-on-chip structure of  claim 1 , wherein said first metal layer comprises a titanium-containing layer under said first electroplated copper layer. 
   
   
       7 . The system-on-chip structure of  claim 1 , wherein said first metal layer comprises a copper seed layer under said first electroplated copper layer. 
   
   
       8 . A system-on-chip structure comprising:
 a silicon substrate;   a metallization structure over said silicon substrate, wherein said metallization structure comprises a first interconnect layer over said silicon substrate and a second interconnect layer over said first interconnect layer;   a first dielectric layer between said first and second interconnect layers;   a passivation layer over said metallization structure and over said first dielectric layer, wherein said passivation layer comprises a nitride layer; and   a capacitor on said passivation layer, wherein said capacitor comprises a lower plate on said passivation layer, an upper plate over said lower plate and a second dielectric layer between said upper and lower plates, wherein said lower plate has a thickness between 0.5 and 20 micrometers, said upper plate has a thickness between 0.5 and 20 micrometers, and said second dielectric layer has a thickness between 500 and 50,000 angstroms, wherein said lower plate comprises a first metal layer and a first electroplated copper layer on said first metal layer, and wherein said upper plate comprises a second metal layer and a second electroplated copper layer on said second metal layer.   
   
   
       9 . The system-on-chip structure of  claim 8 , wherein said second dielectric layer comprises a nitride. 
   
   
       10 . The system-on-chip structure of  claim 8 , wherein said second dielectric layer comprises tantalum oxide. 
   
   
       11 . The system-on-chip structure of  claim 8 , wherein said second dielectric layer comprises an oxide. 
   
   
       12 . The system-on-chip structure of  claim 8 , wherein said first metal layer comprises a titanium-containing layer under said first electroplated copper layer. 
   
   
       13 . The system-on-chip structure of  claim 8 , wherein said first metal layer comprises a copper seed layer under said first electroplated copper layer. 
   
   
       14 . A system-on-chip structure comprising:
 a silicon substrate;   a metallization structure over said silicon substrate, wherein said metallization structure comprises a first interconnect layer over said silicon substrate and a second interconnect layer over said first interconnect layer;   a first dielectric layer between said first and second interconnect layers;   a passivation layer over said metallization structure and over said first dielectric layer, wherein an opening in said passivation layer is over a contact point of said metallization structure, and said contact point is at a bottom of said opening in said passivation layer;   a first capacitor over said passivation layer, wherein said first capacitor comprises a first lower plate over said passivation layer, a first upper plate over said first lower plate and a second dielectric layer between said first upper plate and said first lower plate, wherein said first upper plate is connected to said contact point, and wherein said first upper plate comprises electroplated copper; and   a second capacitor over said passivation layer, wherein said second capacitor comprises a second lower plate over said passivation layer, a second upper plate over said second lower plate and a third dielectric layer between said second upper plate and said second lower plate, wherein said second upper plate is connected to said contact point and to said first upper plate, and wherein said second upper plate comprises electroplated copper.   
   
   
       15 . The system-on-chip structure of  claim 14  further comprising a polymer layer on said passivation layer, wherein said first and second capacitors are further on said polymer layer. 
   
   
       16 . The system-on-chip structure of  claim 14 , wherein said passivation layer comprises a nitride layer. 
   
   
       17 . The system-on-chip structure of  claim 14 , wherein said first lower plate comprises electroplated copper. 
   
   
       18 . The system-on-chip structure of  claim 14 , wherein said first upper plate further comprises a titanium-containing layer under said electroplated copper of said first upper plate. 
   
   
       19 . The system-on-chip structure of  claim 14 , wherein said second dielectric layer comprises an oxide. 
   
   
       20 . The system-on-chip structure of  claim 14 , wherein said second dielectric layer comprises a nitride.