Stacked semiconductor apparatus, system and method of fabrication

Abstract

A stacked semiconductor apparatus and method of fabricating same are disclosed. The apparatus includes upper and lower semiconductor devices having a similar pattern of connection elements. When stacked connected the resulting plurality of semiconductor devices includes a serial connection path traversing the stack, and may also include parallel connection paths, back-side mounted large components, and vertical thermal conduits.

1 . An apparatus, comprising:
 a stacked plurality of semiconductor devices, each device comprising a circuit element disposed on a front-side of a substrate, a back-side connection element disposed on a back-side of the substrate, and a similar connection pattern of connection elements; and   a serial connection path connecting circuit elements respectively disposed on an upper device and a lower device in the stacked plurality of semiconductor devices, the serial connection path comprising a first inter-device connection element disposed on the front-side of the lower device, a first back-side connection element disposed on the back-side of the upper device, and a first vertical connection element extending through the substrate of the upper device,   wherein respective connection elements in the connection pattern of each device comprises at least the first inter-device connection element, the first back-side connection element, and the first vertical connection element are vertically aligned through the stacked plurality of semiconductor devices.   
     
     
         2 . The apparatus of  claim 1 , wherein the first vertical connection element is a through silicon via (TSV). 
     
     
         3 . The apparatus of  claim 1 , wherein the first inter-device connection element is a metal bump. 
     
     
         4 . The apparatus of  claim 3 , wherein the metal bump is used to stack connect the upper device on the lower device. 
     
     
         5 . The apparatus of  claim 1 , wherein the serial connection path further comprises a distribution line connecting a circuit element in the stacked plurality of semiconductor devices with the first inter-device connection element or the first vertical connection element. 
     
     
         6 . The apparatus of  claim 1 , further comprising:
 a parallel connection path connecting the circuit elements disposed on both the upper and lower devices, and comprising a second inter-device connection element disposed on the front-side of the lower device, a second back-side connection element disposed on the back-side of the upper device, and a second vertical connection element extending through the substrate of the upper device,   wherein the second inter-device connection element, the second back-side connection element, and the second vertical connection element in the connection pattern of the upper and lower devices are vertically aligned through the stacked plurality of semiconductor devices.   
     
     
         7 . The apparatus of  claim 1 , further comprising:
 at least one vertical thermal conduit coupling circuit elements disposed on both the upper and lower devices, and comprising;
 a third back-side connection element disposed between the upper and lower devices, 
 a third vertical connection element extending through the substrate of the upper device, and 
 a fourth vertical connection element extending through the substrate of the lower device, wherein the third and fourth vertical connection are vertically aligned through the stacked plurality of semiconductor devices. 
   
     
     
         8 . The apparatus of  claim 7 , wherein the at least one vertical thermal conduit comprises a plurality of vertical thermal conduits forming a thermal bus, and
 the third backside connection element comprises a heat plate element thermally coupling the plurality of vertical thermal conduits.   
     
     
         9 . The apparatus of  claim 1 , wherein each one of the plurality of semiconductor devices is a semiconductor memory device. 
     
     
         10 . The apparatus of  claim 9 , further comprising a mounting substrate on which the stacked plurality of semiconductors is mounted, wherein the mounting substrate comprises a memory controller providing command/address/data (C/A/D) signals associated with read/write operations directed to one or more of the stacked plurality of semiconductor devices. 
     
     
         11 - 18 . (canceled) 
     
     
         19 . An apparatus, comprising:
 a stacked plurality of semiconductor devices, each device comprising a circuit element configured from circuit components and disposed on a front-side of a substrate, a large component disposed on a back-side of the substrate, wherein the large component is fabricated with a size at least an order of magnitude greater than a size of the circuit components, and a similar pattern of connection elements;   wherein at least one internal connection path connects circuit elements respectively disposed on an upper device and a lower device in the stacked plurality of semiconductor devices, the connection path comprising a first inter-device connection element disposed on the front-side of the lower device, a first back-side connection element disposed on the back-side of the upper device, and a first vertical connection element extending through the substrate of the upper device,   wherein respective connection elements in the pattern of connection elements including at least the first inter-device connection element, the first back-side connection element, and the first vertical connection element are vertically aligned through the stacked plurality of semiconductor devices.   
     
     
         20 . The apparatus of  claim 19 , wherein the large component is a large capacitive component coupled to the circuit element by vertical connection elements through the substrate. 
     
     
         21 . The apparatus of  claim 19 , wherein the large component is a large resistive component connected to the circuit element by vertical connection elements through the substrate. 
     
     
         22 . The apparatus of  claim 19 , wherein the large component is a large inductive component connected to the circuit element by vertical connection elements through the substrate. 
     
     
         23 . The apparatus of  claim 19 , wherein the at least one connection path comprises a power signal connection path and a ground connection path. 
     
     
         24 . The apparatus of  claim 20 , wherein the large capacitive component is a de-coupling capacitor, and the at least one connection path comprises a power signal connection path including one vertical connection element and a ground connection path including another vertical connection element, such that the de-coupling capacitor is connected between the power signal connection path and the ground connection path. 
     
     
         25 . The apparatus of  claim 22 , wherein the at least one connection path comprises a power signal connection path including one vertical connection element and a ground connection path including another vertical connection element, such that the large inductive component is connected between the power signal connection path and the ground connection path. 
     
     
         26 - 29 . (canceled) 
     
     
         30 . An apparatus, comprising:
 a stacked plurality of semiconductor devices disposed on a mounting substrate, each device in the stacked plurality of semiconductor devices comprising a circuit element;   at least one vertical thermal conduit traversing the stacked plurality of semiconductor devices and thermally coupling circuit elements respectively disposed on an upper device and a lower device in the stacked plurality of semiconductor devices, the vertical thermal conduit comprising;
 a first vertical connection element extending through the upper device, 
 a second vertical connection element extending through the lower device, wherein the first and second vertical connection elements are vertically aligned in the stacked plurality of semiconductor devices, and 
 a thermal inter-device connection element disposed on the back-side of the upper device; and 
   a heat sink element disposed on the mounting substrate and thermally coupled to the at least one vertical thermal conduit.   
     
     
         31 . The apparatus of  claim 30 , wherein the at least one vertical thermal conduit comprises a plurality of vertical thermal conduits ganged together in a vertical thermal bus. 
     
     
         32 . The apparatus of  claim 30 , wherein the thermal inter-device connection element comprises a heat plate element formed between the upper and lower devices. 
     
     
         33 . The apparatus of  claim 30 , wherein the mounting surface is a printed circuit board. 
     
     
         34 . The apparatus of  claim 33 , wherein the printed circuit board comprises a memory controller and each one of the stacked plurality of semiconductor devices is a semiconductor memory device.