Barrier sequence for use in copper interconnect metallization

Abstract

A method patterns at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at the bottom of the opening. The method then lines the sidewalls and the bottom of the opening with a first Tantalum Nitride layer in a first chamber and forms a Tantalum layer on the first Tantalum Nitride layer in the first chamber. Next, sputter etching on the opening is performed in the first chamber, so as to expose the conductor at the bottom of the opening. A second Tantalum Nitride layer is formed on the conductor, the Tantalum layer, and the first Tantalum Nitride layer, again in the first chamber. After the second Tantalum Nitride layer is formed, the methods herein form a flash layer comprising a Platinum group metal on the second Tantalum Nitride layer in a second, different chamber. After this processing, the structure can be moved to a third chamber where copper is deposited on the flash layer in the opening until the opening is coated with copper in a third chamber.

1 . A structure comprising:
 at least one opening in an insulator layer;   a conductor layer positioned below said insulator layer and at a bottom of said opening;   a first Tantalum Nitride layer on sidewalls of said opening;   a Tantalum layer on said first Tantalum Nitride layer;   a second Tantalum Nitride layer on said Tantalum layer and said conductor layer;   a flash layer comprising a Platinum group metal on said second Tantalum Nitride layer; and   a conductive material filing said opening and positioned on said second Tantalum Nitride layer.   
   
   
       2 . The structure according to  claim 1 , all the limitations of which are incorporated herein, wherein said insulator layer comprises a low-K insulator. 
   
   
       3 . The structure according to  claim 1 , all the limitations of which are incorporated herein, wherein said Tantalum layer is between said first Tantalum Nitride layer and said second Tantalum layer. 
   
   
       4 . The structure according to  claim 1 , all the limitations of which are incorporated herein, wherein said conductive material comprises copper. 
   
   
       5 . The structure according to  claim 4 , all the limitations of which are incorporated herein, wherein said copper creates an electrical connection between said conductor layer and a second conductor layer on an opposite side of said insulator layer. 
   
   
       6 . A structure comprising:
 at least one opening in an insulator layer;   a conductor layer positioned below said insulator layer and at a bottom of said opening;   a first Tantalum Nitride layer on sidewalls of said opening;   a Tantalum layer on said first Tantalum Nitride layer;   a second Tantalum Nitride layer on said Tantalum layer and said conductor layer;   a flash layer comprising a Platinum group metal alloy on said second Tantalum Nitride layer; and   a conductive material filling said opening and positioned on said second Tantalum Nitride layer.   
   
   
       7 . The structure according to  claim 6 , all the limitations of which are incorporated herein, wherein said insulator layer comprises a low-K insulator. 
   
   
       8 . The structure according to  claim 6 , all the limitations of which are incorporated herein, wherein said Tantalum layer is between said first Tantalum Nitride layer and said second Tantalum layer. 
   
   
       9 . The structure according to  claim 6 , all the limitations of which are incorporated herein, wherein said conductive material comprises copper. 
   
   
       10 . The structure according to  claim 9 , all the limitations of which are incorporated herein, wherein said copper creates an electrical connection between said conductor layer and a second conductor layer on an opposite side of said insulator layer. 
   
   
       11 . A method comprising:
 patterning at least one opening in an insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at a bottom of said opening;   lining sidewalls and said bottom of said opening with a first Tantalum Nitride layer;   forming a Tantalum layer on said first Tantalum Nitride layer;   sputter etching said opening so as to expose said conductor at said bottom of said opening;   forming a second Tantalum Nitride layer on said conductor, said Tantalum layer, and said first Tantalum Nitride layer;   forming a flash layer comprising a Platinum group metal on said second Tantalum Nitride layer; and   depositing a copper seed layer on said flash layer in said opening until said opening is coated with copper; and   filling said opening with copper using an electroplating process.   
   
   
       12 . The method according to  claim 11 , all the limitations of which are incorporated herein, wherein said sputter etching comprises an Argon sputter etchback. 
   
   
       13 . The method according to  claim 11 , all the limitations of which are incorporated herein, wherein said sputter etching leaves a portion of said first Tantalum Nitride layer and a portion of said Tantalum layer on said sidewalls of said opening. 
   
   
       14 . The method according to  claim 11 , all the limitations of which are incorporated herein, wherein said Platinum group metal comprises at least one of: Ruthenium, Rhodium, Palladium, Osmium, Iridium, and Platinum. 
   
   
       15 . The method according to  claim 11 , all the limitations of which are incorporated herein, wherein said depositing of said copper seed layer and said filling of said opening with copper creates an electrical connection between said conductor and a second conductor on an opposite side of said insulator layer. 
   
   
       16 . A method comprising:
 patterning at least one opening in an insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at a bottom of said opening;   lining sidewalls and said bottom of said opening with a first Tantalum Nitride layer;   forming a Tantalum layer on said first Tantalum Nitride layer;   sputter etching said opening so as to expose said conductor at said bottom of said opening;   forming a second Tantalum Nitride layer on said conductor, said Tantalum layer, and said first Tantalum Nitride layer;   forming a flash layer comprising a Platinum group metal alloy on said second Tantalum Nitride layer; and   depositing a copper seed layer on said flash layer in said opening until said opening is coated with copper; and   filling said opening with copper using electroplating.   
   
   
       17 . The method according to  claim 16 , all the limitations of which are incorporated herein, wherein said sputter etching comprises an Argon sputter etchback. 
   
   
       18 . The method according to  claim 16 , all the limitations of which are incorporated herein, wherein said sputter etching leaves a portion of said first Tantalum Nitride layer and a portion of said Tantalum layer on said sidewalls of said opening. 
   
   
       19 . The method according to  claim 16 , all the limitations of which are incorporated herein, wherein said Platinum group metal alloy comprises at least one of: Ruthenium, Rhodium, Palladium, Osmium, Iridium, and Platinum. 
   
   
       20 . The method according to  claim 16 , all the limitations of which are incorporated herein, wherein said depositing of said copper seed layer and said filling of said opening with copper creates an electrical connection between said conductor and a second conductor on an opposite side of said insulator layer. 
   
   
       21 . A method comprising:
 patterning at least one opening in a low-K insulator layer of a multi-level integrated circuit structure, such that a copper conductor is exposed at a bottom of said opening;   lining sidewalls and said bottom of said opening with a first Tantalum Nitride layer in a first chamber;   forming a Tantalum layer on said first Tantalum Nitride layer in said first chamber;   sputter etching said opening in said first chamber in said first chamber, so as to expose said conductor at said bottom of said opening;   forming a second Tantalum Nitride layer on said conductor, said Tantalum layer, and said first Tantalum Nitride layer in said first chamber;   forming a flash layer comprising a Platinum group metal on said second Tantalum Nitride layer in a second chamber; and   depositing a copper seed layer on said flash layer in said opening until said opening is coated with copper in a third chamber; and   filling said opening with copper using electroplating.   
   
   
       22 . The method according to  claim 21 , all the limitations of which are incorporated herein, wherein said sputter etching comprises an Argon sputter etchback. 
   
   
       23 . The method according to  claim 21 , all the limitations of which are incorporated herein, wherein said sputter etching leaves a portion of said first Tantalum Nitride layer and a portion of said Tantalum layer on said sidewalls of said opening. 
   
   
       24 . The method according to  claim 21 , all the limitations of which are incorporated herein, wherein said Platinum group metal comprises at least one of: Ruthenium, Rhodium, Palladium, Osmium, Iridium, and Platinum. 
   
   
       25 . The method according to  claim 21 , all the limitations of which are incorporated herein, wherein said depositing of said copper seed layer and said filling of said opening with copper creates an electrical connection between said conductor and a second conductor on an opposite side of said insulator layer.