Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same

Abstract

Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

1 .- 53 . (canceled) 
   
   
       54 . A thin film transistor array panel comprising:
 an insulating substrate;   a plurality of gate lines;   a gate insulating layer covering the gate lines;   a plurality of semiconductors on the gate insulating layer;   a plurality of ohmic contacts on the semiconductors;   a plurality of data lines and source electrodes connected to the data lines, and a plurality of drain electrodes separate from the source electrodes on the ohmic contacts; and   a plurality of conductive electrodes electrically connected to the drain electrodes, wherein the semiconductors except for the portions between the source electrodes and the drain electrodes substantially have the same plane shapes as the data lines, the source electrodes and the drain electrodes.   
   
   
       55 . The thin film transistor array panel of  claim 54 , further comprising a plurality of common electrodes formed on the insulating substrate. 
   
   
       56 . The thin film transistor array panel of  claim 55 , wherein the common electrodes are formed with the same layer as the gate lines. 
   
   
       57 . The thin film transistor array panel of  claim 54 , further comprising a passivation layer covering the data lines and the drain electrodes. 
   
   
       58 . The thin film transistor array panel of  claim 57 , wherein a passivation layer is formed under the conductive electrodes. 
   
   
       59 . The thin film transistor array panel of  claim 54 , the conductive electrodes are pixel electrodes.